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authorMartin Roth <martinroth@chromium.org>2016-10-25 17:31:20 -0700
committerchrome-bot <chrome-bot@chromium.org>2016-11-15 17:41:55 -0800
commit651f8b9acd6a692fa21fa6e0891fffd240522d89 (patch)
tree0dcfa8ffe5aff84a3fb6d9933ed433249d1711e8 /chip
parent897ce78bddb26557a686ab9e756fcf3d6c121271 (diff)
downloadchrome-ec-651f8b9acd6a692fa21fa6e0891fffd240522d89.tar.gz
chip/g to chip/lm4: fix more misspellings in comments
No functional changes. BUG=none BRANCH=none TEST=make buildall passes Change-Id: I0c4fcc900ec0326d6904aa14f298206e62be0fda Signed-off-by: Martin Roth <martinroth@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/403418 Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Diffstat (limited to 'chip')
-rw-r--r--chip/g/flash_config.h2
-rw-r--r--chip/g/i2cm.c6
-rw-r--r--chip/g/i2cs.c8
-rw-r--r--chip/g/loader/main.c2
-rw-r--r--chip/g/spi_master.c2
-rw-r--r--chip/g/sps.c2
-rw-r--r--chip/g/sps.h2
-rw-r--r--chip/g/system.c2
-rw-r--r--chip/g/upgrade_fw.c2
-rw-r--r--chip/g/upgrade_fw.h2
-rw-r--r--chip/g/usb_spi.h4
-rw-r--r--chip/g/usb_upgrade.c4
-rw-r--r--chip/g/watchdog.c2
-rw-r--r--chip/it83xx/clock.c4
-rw-r--r--chip/it83xx/flash.c4
-rw-r--r--chip/it83xx/hwtimer.c2
-rw-r--r--chip/it83xx/i2c.c4
-rw-r--r--chip/lm4/config_chip.h2
-rw-r--r--chip/lm4/lpc.c4
-rw-r--r--chip/lm4/system.c2
-rw-r--r--chip/lm4/watchdog.c2
21 files changed, 32 insertions, 32 deletions
diff --git a/chip/g/flash_config.h b/chip/g/flash_config.h
index 40633e2281..09ddd872d5 100644
--- a/chip/g/flash_config.h
+++ b/chip/g/flash_config.h
@@ -37,7 +37,7 @@ struct g_flash_region {
* properly.
*
* The function is passed an array of the g_flash_region structures of the
- * max_regions size, it fills as many entties as necessary and returns the
+ * max_regions size, it fills as many entries as necessary and returns the
* number of set up entries.
*/
int flash_regions_to_enable(struct g_flash_region *regions,
diff --git a/chip/g/i2cm.c b/chip/g/i2cm.c
index b5f84e1598..b77bd91935 100644
--- a/chip/g/i2cm.c
+++ b/chip/g/i2cm.c
@@ -51,13 +51,13 @@
* I2C_INST_FWBYTESCOUNT = 1 -> 1 byte in FWBYTES (register address)
* I2C_INST_REPEATEDSTART = 1 -> send start bit following write
* I2C_INST_RWDEVADDR = 1 -> send slave address in read mode
- * I2C_INST_RWDEVADDR_RWB = 1 -> read bytes followin slave address
+ * I2C_INST_RWDEVADDR_RWB = 1 -> read bytes following slave address
* I2C_INST_FINALNA = 1 -> ACK read bytes, NACK last byte read
* I2C_INST_FINALSTOP = 1 -> send stop bit
* I2C_INST_DEVADDRVAL = slave address
* I2C_FWBYTES[b7:b0] = out[0] -> register address byte
*
- * Once trasnaction is complete:
+ * Once transaction is complete:
* in[0] = I2C_RW0[b7:b0] -> copy first byte of read into destination
* in[1] = I2C_RW0[b15:b8] -> copy 2nd byte of read into destination
*
@@ -325,7 +325,7 @@ static int i2cm_execute_sequence(int port, int slave_addr, const uint8_t *out,
int rv;
uint32_t inst;
- /* Build sequence instruciton */
+ /* Build sequence instruction */
inst = i2cm_build_sequence(port, slave_addr, out, out_size, in,
in_size, flags);
/* Start transaction */
diff --git a/chip/g/i2cs.c b/chip/g/i2cs.c
index 38668ac932..c1306f6465 100644
--- a/chip/g/i2cs.c
+++ b/chip/g/i2cs.c
@@ -14,10 +14,10 @@
*
* The file holding data written by the master has associated with it a
* register showing where the controller accessed the file last, comparing it
- * with its pervious value tells the driver how many bytes recently written by
+ * with its previous value tells the driver how many bytes recently written by
* the master are there.
*
- * The file holding data to be read by the master has a register associtated
+ * The file holding data to be read by the master has a register associated
* with it showing where was the latest BIT the controller transmitted.
*
* The controller can generate interrupts on three different conditions:
@@ -248,7 +248,7 @@ void i2cs_post_read_fill_fifo(uint8_t *buffer, size_t len)
/* Write in remainder bytes */
for (i = 0; i < remainder_bytes; i++)
word_out_value |= *buffer++ << (8 * (start_offset + i));
- /* Write to fifo regsiter */
+ /* Write to fifo register */
value_addr[addr_offset] = word_out_value;
addr_offset = (addr_offset + 1) & (REGISTER_FILE_MASK >> 2);
/* Account for bytes consumed */
@@ -267,7 +267,7 @@ void i2cs_post_read_fill_fifo(uint8_t *buffer, size_t len)
}
len -= (num_words << 2);
- /* Now proccess remaining bytes (if any), will be <= 3 at this point */
+ /* Now process remaining bytes (if any), will be <= 3 at this point */
remainder_bytes = len;
if (remainder_bytes) {
/* read from HW fifo */
diff --git a/chip/g/loader/main.c b/chip/g/loader/main.c
index e560c9b8b5..e304c30a49 100644
--- a/chip/g/loader/main.c
+++ b/chip/g/loader/main.c
@@ -15,7 +15,7 @@
/*
* This file is a proof of concept stub which will be extended and split into
- * appropriate pieces sortly, when full blown support for cr50 bootrom is
+ * appropriate pieces shortly, when full blown support for cr50 bootrom is
* introduced.
*/
uint32_t sleep_mask;
diff --git a/chip/g/spi_master.c b/chip/g/spi_master.c
index f3ddbd1bdb..a602c518e5 100644
--- a/chip/g/spi_master.c
+++ b/chip/g/spi_master.c
@@ -188,7 +188,7 @@ int spi_enable(int port, int enable)
continue;
#ifndef CONFIG_SPI_MASTER_NO_CS_GPIOS
- /* Make sure CS# is deaserted and disabled. */
+ /* Make sure CS# is deasserted and disabled. */
gpio_set_level(spi_devices[i].gpio_cs, 1);
gpio_set_flags(spi_devices[i].gpio_cs, GPIO_ODR_HIGH);
#endif /* CONFIG_SPI_MASTER_NO_CS_GPIOS */
diff --git a/chip/g/sps.c b/chip/g/sps.c
index 21558a6822..98f4fb54ae 100644
--- a/chip/g/sps.c
+++ b/chip/g/sps.c
@@ -404,7 +404,7 @@ static void sps_receive_callback(uint8_t *data, size_t data_size, int cs_status)
rx_state = spstrx_receiving;
else
/*
- * If we won't be able to receve this much, enter the
+ * If we won't be able to receive this much, enter the
* 'frame finished' state.
*/
rx_state = spstrx_finished;
diff --git a/chip/g/sps.h b/chip/g/sps.h
index f7889b82bd..5f49d8d092 100644
--- a/chip/g/sps.h
+++ b/chip/g/sps.h
@@ -41,7 +41,7 @@ int sps_transmit(uint8_t *data, size_t data_size);
/*
* These functions return zero on success or non-zero on failure (attempt to
* register a callback on top of existing one, or attempt to unregister
- * non-exitisng callback.
+ * non-existing callback.
*
* rx_fifo_threshold value of zero means 'default'.
*/
diff --git a/chip/g/system.c b/chip/g/system.c
index 7ef8e3cf58..4945aee082 100644
--- a/chip/g/system.c
+++ b/chip/g/system.c
@@ -282,7 +282,7 @@ void system_clear_retry_counter(void)
}
/*
- * Check wich of the two cr50 RW images is newer, return true if the first
+ * Check which of the two cr50 RW images is newer, return true if the first
* image is no older than the second one.
*
* Note that RO and RW images use the same header structure. When deciding
diff --git a/chip/g/upgrade_fw.c b/chip/g/upgrade_fw.c
index e9c662877d..19e89f6507 100644
--- a/chip/g/upgrade_fw.c
+++ b/chip/g/upgrade_fw.c
@@ -190,7 +190,7 @@ void fw_upgrade_command_handler(void *body,
/*
* If there have been any problems when determining the valid
- * secitons offsets/sizes - return an error code.
+ * Sections offsets/sizes - return an error code.
*/
if (!valid_sections.ro_top_offset ||
!valid_sections.rw_top_offset) {
diff --git a/chip/g/upgrade_fw.h b/chip/g/upgrade_fw.h
index 7d0fc3324b..cab1f083ca 100644
--- a/chip/g/upgrade_fw.h
+++ b/chip/g/upgrade_fw.h
@@ -81,7 +81,7 @@ struct signed_header_version {
* just as to any other block of the transfer sequence.
*
* It became clear that there is a need to be able to enhance the upgrade
- * protocol, while stayng backwards compatible.
+ * protocol, while staying backwards compatible.
*
* All newer protocol versions (starting with version 2) respond to the very
* first packet with an 8 byte or larger response, where the first 4 bytes are
diff --git a/chip/g/usb_spi.h b/chip/g/usb_spi.h
index 6aa6c203ea..c1dfad519c 100644
--- a/chip/g/usb_spi.h
+++ b/chip/g/usb_spi.h
@@ -110,7 +110,7 @@ struct usb_spi_config {
struct usb_spi_state *state;
/*
- * Interface and endpoint indicies.
+ * Interface and endpoint indices.
*/
int interface;
int endpoint;
@@ -123,7 +123,7 @@ struct usb_spi_config {
/*
- * Pointer to tx and rx queus and bounce buffer.
+ * Pointer to tx and rx queues and bounce buffer.
*/
uint8_t *buffer;
struct consumer const consumer;
diff --git a/chip/g/usb_upgrade.c b/chip/g/usb_upgrade.c
index 493cd7cc92..1e1fb82957 100644
--- a/chip/g/usb_upgrade.c
+++ b/chip/g/usb_upgrade.c
@@ -74,7 +74,7 @@ static uint32_t block_size;
static uint32_t block_index;
/*
- * Verify that the contens of the USB rx queue is a valid transfer start
+ * Verify that the contents of the USB rx queue is a valid transfer start
* message from host, and if so - save its contents in the passed in
* update_frame_header structure.
*/
@@ -157,7 +157,7 @@ static void upgrade_out_handler(struct consumer const *consumer, size_t count)
if (!valid_transfer_start(consumer, count, &u.upfr)) {
/*
- * Someting is wrong, this payload is not a valid
+ * Something is wrong, this payload is not a valid
* update start PDU. Let'w indicate this by returning
* a single byte error code.
*/
diff --git a/chip/g/watchdog.c b/chip/g/watchdog.c
index 0c565f3850..edfe61113b 100644
--- a/chip/g/watchdog.c
+++ b/chip/g/watchdog.c
@@ -33,7 +33,7 @@ void IRQ_HANDLER(GC_IRQNUM_WATCHDOG0_WDOGINT)(void)
asm volatile("mov r0, lr\n"
"mov r1, sp\n"
/* Must push registers in pairs to keep 64-bit aligned
- * stack for ARM EABI. This also conveninently saves
+ * stack for ARM EABI. This also conveniently saves
* R0=LR so we can pass it to task_resched_if_needed. */
"push {r0, lr}\n"
/* We've lowered our runlevel, so just rebooting the ARM
diff --git a/chip/it83xx/clock.c b/chip/it83xx/clock.c
index c353c7b326..b5638f2bbc 100644
--- a/chip/it83xx/clock.c
+++ b/chip/it83xx/clock.c
@@ -147,7 +147,7 @@ void __ram_code clock_pll_changed(void)
IT83XX_ECPM_SCDCR0 = (2 << 4);
/* JTAG and EC */
IT83XX_ECPM_SCDCR3 = (pll_div_jtag << 4) | pll_div_ec;
- /* EC sleep after stanbdy instructioin */
+ /* EC sleep after standby instruction */
clock_ec_pll_ctrl(EC_PLL_SLEEP);
/* Global interrupt enable */
asm volatile ("setgie.e");
@@ -157,7 +157,7 @@ void __ram_code clock_pll_changed(void)
asm volatile ("setgie.d");
/* New FND clock frequency */
IT83XX_ECPM_SCDCR0 = (pll_div_fnd << 4);
- /* EC doze after stanbdy instructioin */
+ /* EC doze after standby instruction */
clock_ec_pll_ctrl(EC_PLL_DOZE);
}
diff --git a/chip/it83xx/flash.c b/chip/it83xx/flash.c
index 2df59fdf17..d80c9dfd57 100644
--- a/chip/it83xx/flash.c
+++ b/chip/it83xx/flash.c
@@ -539,13 +539,13 @@ static void flash_code_static_dma(void)
/*
* Enable ILM
* Set the logic memory address(flash code of RO/RW) in eflash
- * by programing the register SCARx bit19-bit0.
+ * by programming the register SCARx bit19-bit0.
*/
IT83XX_SMFI_SCAR2L = FLASH_DMA_START & 0xFF;
IT83XX_SMFI_SCAR2M = (FLASH_DMA_START >> 8) & 0xFF;
IT83XX_SMFI_SCAR2H = (FLASH_DMA_START >> 16) & 0x0F;
/*
- * Validate Direct-map SRAM function by programing
+ * Validate Direct-map SRAM function by programming
* register SCARx bit20=0
*/
IT83XX_SMFI_SCAR2H &= ~0x10;
diff --git a/chip/it83xx/hwtimer.c b/chip/it83xx/hwtimer.c
index 8016ed4a7c..915fe3f6dd 100644
--- a/chip/it83xx/hwtimer.c
+++ b/chip/it83xx/hwtimer.c
@@ -166,7 +166,7 @@ int __hw_clock_source_init(uint32_t start_t)
IT83XX_ETWD_ETXCTRL(FREE_EXT_TIMER_L) |= (1 << 3);
/* init free running timer (timer 4, TIMER_H), clock source is 8mhz */
ext_timer_ms(FREE_EXT_TIMER_H, EXT_PSR_8M_HZ, 0, 1, 0xffffffff, 1, 1);
- /* 1us counter settiing (timer 3, TIMER_L) */
+ /* 1us counter setting (timer 3, TIMER_L) */
ext_timer_ms(FREE_EXT_TIMER_L, EXT_PSR_8M_HZ, 1, 0, 7, 1, 1);
__hw_clock_source_set(start_t);
/* init event timer */
diff --git a/chip/it83xx/i2c.c b/chip/it83xx/i2c.c
index b76c04ba1e..da45735cf1 100644
--- a/chip/it83xx/i2c.c
+++ b/chip/it83xx/i2c.c
@@ -201,7 +201,7 @@ struct i2c_port_data {
int err; /* Error code, if any */
uint8_t addr; /* address of device */
uint32_t timeout_us; /* Transaction timeout, or 0 to use default */
- uint8_t freq; /* Freqency setting */
+ uint8_t freq; /* Frequency setting */
enum i2c_ch_status i2ccs;
/* Task waiting on port, or TASK_ID_INVALID if none. */
@@ -887,7 +887,7 @@ static void i2c_freq_changed(void)
* (1 / (1000 x freq)) x (1 / 2)) - 2
*/
if (freq) {
- /* Get SMBus clock devide value */
+ /* Get SMBus clock divide value */
clk_div = (IT83XX_ECPM_SCDCR2 & 0x0F) + 1;
/* Calculate PSR value */
psr = (PLL_CLOCK /
diff --git a/chip/lm4/config_chip.h b/chip/lm4/config_chip.h
index ac12470097..31ee2f6b9b 100644
--- a/chip/lm4/config_chip.h
+++ b/chip/lm4/config_chip.h
@@ -9,7 +9,7 @@
/* CPU core BFD configuration */
#include "core/cortex-m/config_core.h"
-/* 16.000 Mhz internal oscillator frequency (PIOSC) */
+/* 16.000 MHz internal oscillator frequency (PIOSC) */
#define INTERNAL_CLOCK 16000000
/* Number of IRQ vectors on the NVIC */
diff --git a/chip/lm4/lpc.c b/chip/lm4/lpc.c
index 646ad30150..4da0f8e1f8 100644
--- a/chip/lm4/lpc.c
+++ b/chip/lm4/lpc.c
@@ -813,7 +813,7 @@ static void lpc_init(void)
#endif /* CONFIG_UART_HOST */
/*
- * Unmaksk LPC bus reset interrupt. This lets us monitor the PCH
+ * Unmask LPC bus reset interrupt. This lets us monitor the PCH
* PLTRST# signal for debugging.
*/
LM4_LPC_LPCIM |= (1 << 31);
@@ -833,7 +833,7 @@ static void lpc_init(void)
/*
* Ensure the EC (slave) has control of the memory-mapped I/O space.
- * Once the EC has won arbtration for the memory-mapped space, it will
+ * Once the EC has won arbitration for the memory-mapped space, it will
* keep control of it until it writes the last byte in the space.
* (That never happens; we can't use the last byte in the space because
* ACPI can't see it anyway.)
diff --git a/chip/lm4/system.c b/chip/lm4/system.c
index 3f39da0a32..cb1cf8cef0 100644
--- a/chip/lm4/system.c
+++ b/chip/lm4/system.c
@@ -301,7 +301,7 @@ void system_set_rtc_alarm(uint32_t seconds, uint32_t microseconds)
* Wait for the write to commit. This ensures that the RTC interrupt
* actually gets enabled. This is important if we're about to switch
* the system to the 30 kHz oscillator, which might prevent the write
- * from comitting.
+ * from committing.
*/
wait_for_hibctl_wc();
}
diff --git a/chip/lm4/watchdog.c b/chip/lm4/watchdog.c
index 565ce69fd4..f743077441 100644
--- a/chip/lm4/watchdog.c
+++ b/chip/lm4/watchdog.c
@@ -31,7 +31,7 @@ void IRQ_HANDLER(LM4_IRQ_WATCHDOG)(void)
asm volatile("mov r0, lr\n"
"mov r1, sp\n"
/* Must push registers in pairs to keep 64-bit aligned
- * stack for ARM EABI. This also conveninently saves
+ * stack for ARM EABI. This also conveniently saves
* R0=LR so we can pass it to task_resched_if_needed. */
"push {r0, lr}\n"
"bl watchdog_trace\n"