diff options
author | Johnnie Chan <johnniec@chromium.org> | 2016-08-13 00:04:30 -0700 |
---|---|---|
committer | chrome-bot <chrome-bot@chromium.org> | 2016-08-24 17:40:39 -0700 |
commit | dbd62c36da1fa1960a050cf569b93deaa194cea7 (patch) | |
tree | a1da9cd1239829b49c57a70b5e5bb66402018e3a /chip | |
parent | c5bd6d98b9c0799b2c7409d95af980fcdc1e44ea (diff) | |
download | chrome-ec-dbd62c36da1fa1960a050cf569b93deaa194cea7.tar.gz |
Modified flash API batch write logic to respect row boundaries.
* Added MACRO for specifying row size of flash device.
* Set chip/g specific values for flash row size.
The flash API for g/chip will segment large write operations into a
maximum of 32 word blocks for batch writes to flash memory. Prior to
the change in this commit, the segmentation will adhere to avoiding
crossing page boundaries (2048B) but will not respect row boundaries
(256B). The flash controller will reject any write op that crosses a
row boundary and set a row boundary violation code on its error
register.
BRANCH=none
BUG=b:30819377
TEST=make BOARD=haven_dev
Change-Id: I489122ec0f0db6374dd373a1385c3012bdface20
Reviewed-on: https://chromium-review.googlesource.com/371003
Commit-Ready: Bill Richardson <wfrichar@chromium.org>
Commit-Ready: Johnnie Chan <johnniec@google.com>
Tested-by: Johnnie Chan <johnniec@google.com>
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Diffstat (limited to 'chip')
-rw-r--r-- | chip/g/config_chip.h | 2 | ||||
-rw-r--r-- | chip/g/flash.c | 6 |
2 files changed, 5 insertions, 3 deletions
diff --git a/chip/g/config_chip.h b/chip/g/config_chip.h index f0c508e2e9..b531f5d8b3 100644 --- a/chip/g/config_chip.h +++ b/chip/g/config_chip.h @@ -22,6 +22,8 @@ #define CONFIG_FLASH_WRITE_SIZE 4 /* min write size (bytes) */ /* But we have a 32-word buffer for writing multiple adjacent cells */ #define CONFIG_FLASH_WRITE_IDEAL_SIZE 128 /* best write size (bytes) */ +/* The flash controller prevents bulk writes that cross row boundaries */ +#define CONFIG_FLASH_ROW_SIZE 256 /* row size */ /* Describe the flash layout */ #define CONFIG_PROGRAM_MEMORY_BASE 0x40000 diff --git a/chip/g/flash.c b/chip/g/flash.c index 6a329756a7..870f76ef34 100644 --- a/chip/g/flash.c +++ b/chip/g/flash.c @@ -311,10 +311,10 @@ static int flash_physical_write_internal(int byte_offset, int is_info_bank, num = MIN(num_bytes, CONFIG_FLASH_WRITE_IDEAL_SIZE); /* * Make sure that the write operation will not go - * past a CONFIG_FLASH_ERASE_SIZE boundary. + * past a CONFIG_FLASH_ROW_SIZE boundary. */ - num = MIN(num, CONFIG_FLASH_ERASE_SIZE - - byte_offset % CONFIG_FLASH_ERASE_SIZE); + num = MIN(num, CONFIG_FLASH_ROW_SIZE - + byte_offset % CONFIG_FLASH_ROW_SIZE); ret = write_batch(byte_offset, is_info_bank, num / 4, /* word count */ |