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author | Namyoon Woo <namyoon@chromium.org> | 2019-12-09 14:34:55 -0800 |
---|---|---|
committer | Commit Bot <commit-bot@chromium.org> | 2020-02-22 01:46:39 +0000 |
commit | 5a8a856b0a942d3b982ef28324a924db3c7d9f40 (patch) | |
tree | ac82cccef343c83adc300d1e7c2c9bb41df095e0 /chip | |
parent | 9d9c4ca2342d09ccf241173d36d3cf2b16ed3c41 (diff) | |
download | chrome-ec-5a8a856b0a942d3b982ef28324a924db3c7d9f40.tar.gz |
EC-CR50 communication
This patch supports EC-CR50 communication.
EC activates EC-CR50 communication by setting high DIOB3, and send
a command packet to CR50 through UART_EC_TX_CR50_RX. Cr50 processes
the packet, and sends a response packet back to EC. EC deactivates
EC-CR50 communication by putting low DIOB3.
This patch supports two kinds of EC-CR50 commands:
- CR50_COMM_CMD_SET_BOOT_MODE
- CR50_COMM_CMD_VERIFY_HASH
Cr50 stores some of EC-EFS context in a powerdown register before
deep sleep and restores it after wakeup.
This patch increases flash usage by 1456 bytes.
BUG=b:119329144
BRANCH=cr50
TEST=Checked "ec_comm" console command on Octopus and
reworked Helios.
Checked uart_stress_tester.py running without character loss.
Change-Id: I23e90b9f3e860a3d198dcee718d7d11080d06e40
Signed-off-by: Namyoon Woo <namyoon@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1961145
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Diffstat (limited to 'chip')
-rw-r--r-- | chip/g/init_chip.h | 1 | ||||
-rw-r--r-- | chip/g/usart.c | 35 |
2 files changed, 26 insertions, 10 deletions
diff --git a/chip/g/init_chip.h b/chip/g/init_chip.h index 506dfeab21..a5c08cd3d9 100644 --- a/chip/g/init_chip.h +++ b/chip/g/init_chip.h @@ -23,6 +23,7 @@ * SCRATCH17 - deep sleep count * SCRATCH18 - Preserving USB_DCFG through deep sleep * SCRATCH19 - Preserving USB data sequencing PID through deep sleep + * SCRATCH20 - Preserving EC-EFS context * * PWRDN_SCRATCH 28 - 31 - Reserved for boot rom */ diff --git a/chip/g/usart.c b/chip/g/usart.c index b597cb3f93..4329a673bc 100644 --- a/chip/g/usart.c +++ b/chip/g/usart.c @@ -167,7 +167,7 @@ void get_data_from_usb(struct usart_config const *config) #ifdef BOARD_CR50 if (config->uart == UART_EC) { /* - * If USB-to-UART bridging is disabled, drop all input data. + * If USB-to-UART bridging is disabled, do not forward data. * Otherwise, data could be pushed into UART TX FIFO, and * transferred to EC eventually once EC-CR50 communication * enables EC UART. @@ -204,14 +204,35 @@ void send_data_to_usb(struct usart_config const *config) q_room = queue_space(uart_in); - if (!q_room) - return; - mask = uart_in->buffer_units_mask; tail = uart_in->state->tail & mask; count = 0; #ifdef BOARD_CR50 + if (ec_comm_is_uart_in_packet_mode(uart)) { + /* + * Even if UART-to-USB data queue is full (count == q_room), + * It should drain UART queue, so that an EC packet + * can be processed. In this case, EC console data + * shall be lost anyway. + */ + while (uartn_rx_available(uart)) { + uint8_t ch = uartn_read_char(uart); + + if (ec_comm_process_packet(ch)) + continue; + + if ((count != q_room) && ec_bridge_enabled_) { + uart_in->buffer[tail] = ch; + tail = (tail + 1) & mask; + count++; + } + } + if (count) + queue_advance_tail(uart_in, count); + return; + } + /* * If UART-to-USB bridging is not allowed, do not put any output * data to uart_in queue. @@ -219,12 +240,6 @@ void send_data_to_usb(struct usart_config const *config) if ((uart == UART_EC) && !ec_bridge_enabled_) return; #endif /* BOARD_CR50 */ - /* - * TODO(b/119329144): Process packet data separately, - * and filter console data based on ccd capability. - * if (ec_comm_is_uart_in_packet_mode(uart)) - * ... - */ while ((count != q_room) && uartn_rx_available(uart)) { uart_in->buffer[tail] = uartn_read_char(uart); |