ec: change usage of dummy

Google is working to change its source code to use more inclusive
language. To that end, replace the term "dummy" with inclusive
alternatives.

BUG=b:162781382
BRANCH=None
TEST=make -j buildall
     `grep -ir dummy *`
      The only results are in "private/nordic_keyboard/sdk8.0.0"
      which is not our code.

Signed-off-by: Sam Hurst <shurst@google.com>
Change-Id: I6a42183d998e4db4bb61625f962867fda10722e2
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2335737
Reviewed-by: Tom Hughes <tomhughes@chromium.org>

47 files changed, 116 insertions, 116 deletions

diff --git a/chip/host/clock.c b/chip/host/clock.c
index 1bb3d56dfb..2c3c48661e 100644
--- a/chip/host/clock.c
+++ b/chip/host/clock.c
@@ -2,7 +2,7 @@
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
- * Dummy clock driver for unit test.
+ * Mock clock driver for unit test.
  */
 
 #include "clock.h"
diff --git a/chip/host/i2c.c b/chip/host/i2c.c
index f474c38ef1..8e6f086b4f 100644
--- a/chip/host/i2c.c
+++ b/chip/host/i2c.c
@@ -2,7 +2,7 @@
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
- * Dummy I2C driver for unit test.
+ * Mock I2C driver for unit test.
  */
 
 #include "hooks.h"
diff --git a/chip/host/spi_master.c b/chip/host/spi_master.c
index 83bde96163..1900e7b7a8 100644
--- a/chip/host/spi_master.c
+++ b/chip/host/spi_master.c
@@ -2,7 +2,7 @@
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
- * Dummy Master SPI driver for unit test.
+ * Mock Master SPI driver for unit test.
  */
 
 #include <stdint.h>
diff --git a/chip/host/trng.c b/chip/host/trng.c
index d90415df71..8407aa6ea1 100644
--- a/chip/host/trng.c
+++ b/chip/host/trng.c
@@ -3,7 +3,7 @@
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  *
- * Dummy TRNG driver for unit test.
+ * Mock TRNG driver for unit test.
  *
  * Although a TRNG is designed to be anything but predictable,
  * this implementation strives to be as predictable and defined
diff --git a/chip/ish/gpio.c b/chip/ish/gpio.c
index 3d374f3cb8..6c7a27e1e7 100644
--- a/chip/ish/gpio.c
+++ b/chip/ish/gpio.c
@@ -21,7 +21,7 @@ test_mockable int gpio_get_level(enum gpio_signal signal)
 	const struct gpio_info *g = gpio_list + signal;
 
 	/* Unimplemented GPIOs shouldn't do anything */
-	if (g->port == DUMMY_GPIO_BANK)
+	if (g->port == UNIMPLEMENTED_GPIO_BANK)
 		return 0;
 
 	return  !!(ISH_GPIO_GPLR & g->mask);
@@ -32,7 +32,7 @@ void gpio_set_level(enum gpio_signal signal, int value)
 	const struct gpio_info *g = gpio_list + signal;
 
 	/* Unimplemented GPIOs shouldn't do anything */
-	if (g->port == DUMMY_GPIO_BANK)
+	if (g->port == UNIMPLEMENTED_GPIO_BANK)
 		return;
 
 	if (value)
@@ -44,7 +44,7 @@ void gpio_set_level(enum gpio_signal signal, int value)
 void gpio_set_flags_by_mask(uint32_t port, uint32_t mask, uint32_t flags)
 {
 	/* Unimplemented GPIOs shouldn't do anything */
-	if (port == DUMMY_GPIO_BANK)
+	if (port == UNIMPLEMENTED_GPIO_BANK)
 		return;
 
 	/* ISH does not support level-trigger interrupts; only edge. */
@@ -92,7 +92,7 @@ int gpio_enable_interrupt(enum gpio_signal signal)
 	const struct gpio_info *g = gpio_list + signal;
 
 	/* Unimplemented GPIOs shouldn't do anything */
-	if (g->port == DUMMY_GPIO_BANK)
+	if (g->port == UNIMPLEMENTED_GPIO_BANK)
 		return EC_SUCCESS;
 
 	ISH_GPIO_GIMR |= g->mask;
diff --git a/chip/ish/registers.h b/chip/ish/registers.h
index 5942a89083..258abe33ef 100644
--- a/chip/ish/registers.h
+++ b/chip/ish/registers.h
@@ -13,7 +13,7 @@
 #include "compile_time_macros.h"
 
 /* ISH GPIO has only one port */
-#define DUMMY_GPIO_BANK -1
+#define UNIMPLEMENTED_GPIO_BANK -1
 
 /*
  * ISH3.0 has 3 controllers. Locking must occur by-controller (not by-port).
diff --git a/chip/it83xx/registers.h b/chip/it83xx/registers.h
index 8a4fc99cf2..1d654295d2 100644
--- a/chip/it83xx/registers.h
+++ b/chip/it83xx/registers.h
@@ -854,7 +854,7 @@ static const struct gpio_reg_t gpio_group_to_reg[] = {
 };
 BUILD_ASSERT(ARRAY_SIZE(gpio_group_to_reg) == (COUNT));
 
-#define DUMMY_GPIO_BANK GPIO_A
+#define UNIMPLEMENTED_GPIO_BANK GPIO_A
 
 #define IT83XX_GPIO_DATA(port)                 \
 	REG8(gpio_group_to_reg[port].reg_gpdr)
diff --git a/chip/it83xx/spi.c b/chip/it83xx/spi.c
index 82f64c65c8..4c70634bc2 100644
--- a/chip/it83xx/spi.c
+++ b/chip/it83xx/spi.c
@@ -265,7 +265,7 @@ void spi_slv_int_handler(void)
 	 * There is a limitation that Rx FIFO starts dropping
 	 * data when the CPU access the the FIFO. So we will
 	 * wait the data until Rx byte reach then to parse.
-	 * The Rx FIFO to reach is dummy data generated by
+	 * The Rx FIFO to reach is mock data generated by
 	 * generate clock that is not the bytes sent from
 	 * the host.
 	 */
@@ -291,7 +291,7 @@ static void spi_init(void)
 	 * bit6 : SPI pin function select (0b:Enable, 1b:Mask)
 	 */
 	IT83XX_GCTRL_MCCR3 |= IT83XX_GCTRL_SPISLVPFE;
-	/* Set dummy blcoked byte */
+	/* Set unused blocked byte */
 	IT83XX_SPI_HPR2 = 0x00;
 	/* Set FIFO data target count */
 	IT83XX_SPI_FTCB1R = (SPI_RX_MAX_FIFO_SIZE >> 8) & 0xff;
diff --git a/chip/lm4/adc_chip.h b/chip/lm4/adc_chip.h
index 8cf033b128..b43bec2da3 100644
--- a/chip/lm4/adc_chip.h
+++ b/chip/lm4/adc_chip.h
@@ -42,7 +42,7 @@ extern const struct adc_t adc_channels[];
 /* Just plain id mapping for code readability */
 #define LM4_AIN(x) (x)
 
-/* Dummy value for "channel" in adc_t if we don't have an external channel. */
+/* Mock value for "channel" in adc_t if we don't have an external channel. */
 #define LM4_AIN_NONE (-1)
 
 #endif /* __CROS_EC_ADC_CHIP_H */
diff --git a/chip/lm4/lpc.c b/chip/lm4/lpc.c
index 0c672bd63a..5b146ba32a 100644
--- a/chip/lm4/lpc.c
+++ b/chip/lm4/lpc.c
@@ -768,7 +768,7 @@ static void lpc_init(void)
 	while (!(LM4_LPC_ST(LPC_CH_MEMMAP) & 0x10)) {
 		/* Clear HW1ST */
 		LM4_LPC_ST(LPC_CH_MEMMAP) &= ~0x40;
-		/* Do a dummy slave write; this should cause SW1ST to be set */
+		/* Do a slave write; this should cause SW1ST to be set */
 		*LPC_POOL_MEMMAP = *LPC_POOL_MEMMAP;
 	}
 
diff --git a/chip/lm4/registers.h b/chip/lm4/registers.h
index da4741a344..0c59da19f6 100644
--- a/chip/lm4/registers.h
+++ b/chip/lm4/registers.h
@@ -489,7 +489,7 @@ enum clock_gate_offsets {
 #define GPIO_P LM4_GPIO_P
 #define GPIO_Q LM4_GPIO_Q
 
-#define DUMMY_GPIO_BANK GPIO_A
+#define UNIMPLEMENTED_GPIO_BANK GPIO_A
 
 /* Value to write to LM4_GPIO_LOCK to unlock writes */
 #define LM4_GPIO_LOCK_UNLOCK          0x4c4f434b
diff --git a/chip/lm4/spi.c b/chip/lm4/spi.c
index 6df3d9e3ee..be988b78a0 100644
--- a/chip/lm4/spi.c
+++ b/chip/lm4/spi.c
@@ -65,12 +65,12 @@ int spi_transaction(const struct spi_device_t *spi_device,
 	int totallen = txlen + rxlen;
 	int txcount = 0, rxcount = 0;
 	static struct mutex spi_mutex;
-	volatile uint32_t dummy  __attribute__((unused));
+	volatile uint32_t unused  __attribute__((unused));
 
 	mutex_lock(&spi_mutex);
 	/* Empty the receive FIFO */
 	while (LM4_SSI_SR(0) & LM4_SSI_SR_RNE)
-		dummy = LM4_SSI_DR(0);
+		unused = LM4_SSI_DR(0);
 
 	/* Start transaction.  Need to do this explicitly because the LM4
 	 * SSI controller pulses its frame select every byte, and the EEPROM
@@ -85,7 +85,7 @@ int spi_transaction(const struct spi_device_t *spi_device,
 			if (rxcount < txlen) {
 				/* Throw away bytes received while we were
 				   transmitting */
-				dummy = LM4_SSI_DR(0);
+				unused = LM4_SSI_DR(0);
 			} else
 				*(rxdata++) = LM4_SSI_DR(0);
 			rxcount++;
@@ -96,7 +96,7 @@ int spi_transaction(const struct spi_device_t *spi_device,
 			if (txcount < txlen)
 				LM4_SSI_DR(0) = *(txdata++);
 			else {
-				/* Clock out dummy byte so we can clock in the
+				/* Clock out unused byte so we can clock in the
 				 * response byte */
 				LM4_SSI_DR(0) = 0;
 			}
diff --git a/chip/lm4/watchdog.c b/chip/lm4/watchdog.c
index 910cb87e03..50f122bf02 100644
--- a/chip/lm4/watchdog.c
+++ b/chip/lm4/watchdog.c
@@ -65,7 +65,7 @@ void watchdog_reload(void)
 	if (status) {
 		LM4_WATCHDOG_ICR(0) = status;
 		/* That doesn't seem to unpend the watchdog interrupt (even if
-		 * we do dummy writes to force the write to be committed), so
+		 * we do writes to force the write to be committed), so
 		 * explicitly unpend the interrupt before re-enabling it. */
 		task_clear_pending_irq(LM4_IRQ_WATCHDOG);
 		task_enable_irq(LM4_IRQ_WATCHDOG);
diff --git a/chip/max32660/registers.h b/chip/max32660/registers.h
index 8a2a072898..e444888fa0 100644
--- a/chip/max32660/registers.h
+++ b/chip/max32660/registers.h
@@ -142,7 +142,7 @@ extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock)  */
 #define GPIO_3 PORT_3 /**< Port 3  Define*/
 #define GPIO_4 PORT_4 /**< Port 4  Define*/
 
-#define DUMMY_GPIO_BANK GPIO_0
+#define UNIMPLEMENTED_GPIO_BANK GPIO_0
 
 /******************************************************************************/
 /*                                                                        I2C */
diff --git a/chip/mchp/clock.c b/chip/mchp/clock.c
index ad8c47d38e..9fdb058898 100644
--- a/chip/mchp/clock.c
+++ b/chip/mchp/clock.c
@@ -94,7 +94,7 @@ int clock_get_freq(void)
  */
 void clock_init(void)
 {
-	int __attribute__((unused)) dummy;
+	int __attribute__((unused)) unused;
 
 	trace0(0, MEC, 0, "Clock Init");
 
@@ -117,8 +117,8 @@ void clock_init(void)
 #endif
 	trace0(0, MEC, 0, "PLL OSC is Locked");
 #ifndef LFW
-	dummy = shared_mem_size();
-	trace11(0, MEC, 0, "Shared Memory size = 0x%08x", (uint32_t)dummy);
+	unused = shared_mem_size();
+	trace11(0, MEC, 0, "Shared Memory size = 0x%08x", (uint32_t)unused);
 #endif
 }
 
diff --git a/chip/mchp/config_chip.h b/chip/mchp/config_chip.h
index 7a0008958c..747a10a8b8 100644
--- a/chip/mchp/config_chip.h
+++ b/chip/mchp/config_chip.h
@@ -44,7 +44,7 @@
  * MCHP I2C controller is master-slave capable and requires
  * a slave address be programmed even if used as master only.
  * Each I2C controller can respond to two slave address.
- * Define dummy slave addresses that aren't used on the I2C port(s)
+ * Define fake slave addresses that aren't used on the I2C port(s)
  * connected to each controller.
  */
 #define CONFIG_MCHP_I2C0_SLAVE_ADDRS	0xE3E1
diff --git a/chip/mchp/dma.c b/chip/mchp/dma.c
index 6c9ed8dd47..982dfa8122 100644
--- a/chip/mchp/dma.c
+++ b/chip/mchp/dma.c
@@ -43,7 +43,7 @@ void dma_disable(enum dma_channel channel)
 void dma_disable_all(void)
 {
 	uint16_t ch;
-	uint32_t dummy = 0;
+	uint32_t unused = 0;
 
 	for (ch = 0; ch < MCHP_DMAC_COUNT; ch++) {
 		/* Abort any current transfer. */
@@ -55,7 +55,7 @@ void dma_disable_all(void)
 
 	/* Soft-reset the block. */
 	MCHP_DMA_MAIN_CTRL = MCHP_DMA_MAIN_CTRL_SRST;
-	dummy += MCHP_DMA_MAIN_CTRL;
+	unused += MCHP_DMA_MAIN_CTRL;
 	MCHP_DMA_MAIN_CTRL = MCHP_DMA_MAIN_CTRL_ACT;
 }
 
diff --git a/chip/mchp/gpspi.c b/chip/mchp/gpspi.c
index f8b556d389..4edf57ee11 100644
--- a/chip/mchp/gpspi.c
+++ b/chip/mchp/gpspi.c
@@ -56,14 +56,14 @@ static int gpspi_wait_byte(const int ctrl)
 /* NOTE: auto-read must be disabled before calling this routine! */
 static void gpspi_rx_fifo_clean(const int ctrl)
 {
-	uint8_t dummy = 0;
+	uint8_t unused = 0;
 
 	/* If ACTIVE and/or RXFF then clean it */
 	if ((MCHP_SPI_SR(ctrl) & 0x4) == 0x4)
-		dummy += MCHP_SPI_RD(ctrl);
+		unused += MCHP_SPI_RD(ctrl);
 
 	if ((MCHP_SPI_SR(ctrl) & 0x2) == 0x2)
-		dummy += MCHP_SPI_RD(ctrl);
+		unused += MCHP_SPI_RD(ctrl);
 }
 /*
  * NOTE: auto-read must be disabled before calling this routine!
@@ -73,7 +73,7 @@ static int gpspi_tx(const int ctrl, const uint8_t *txdata, int txlen)
 {
 	int i;
 	int ret;
-	uint8_t dummy = 0;
+	uint8_t unused = 0;
 
 	gpspi_rx_fifo_clean(ctrl);
 
@@ -83,7 +83,7 @@ static int gpspi_tx(const int ctrl, const uint8_t *txdata, int txlen)
 		ret = gpspi_wait_byte(ctrl);
 		if (ret != EC_SUCCESS)
 			break;
-		dummy += MCHP_SPI_RD(ctrl);
+		unused += MCHP_SPI_RD(ctrl);
 	}
 
 	return ret;
diff --git a/chip/mchp/i2c.c b/chip/mchp/i2c.c
index ab2c75c754..da7136a6b2 100644
--- a/chip/mchp/i2c.c
+++ b/chip/mchp/i2c.c
@@ -454,7 +454,7 @@ static int wait_byte_done(int controller, uint8_t mask, uint8_t expected)
  * Switch port by reset and reconfigure to handle cases where
  * the slave on current port is driving line(s) low.
  * NOTE: I2C hardware reset only requires one AHB clock, back to back
- * writes is OK but we added a dummy write as insurance.
+ * writes is OK but we added an extra write as insurance.
  */
 static void select_port(int port, int controller)
 {
@@ -465,7 +465,7 @@ static void select_port(int port, int controller)
 		return;
 
 	MCHP_I2C_CONFIG(controller) |= BIT(9);
-	MCHP_EC_ID_RO = 0; /* dummy write to read-only as delay */
+	MCHP_EC_ID_RO = 0; /* extra write to read-only as delay */
 	MCHP_I2C_CONFIG(controller) &= ~BIT(9);
 	configure_controller(controller, port_sel, i2c_ports[port].kbps);
 }
@@ -651,7 +651,7 @@ static int i2c_mrx_start(int ctrl)
 		return rv;
 	}
 	/* if STOP requested and last 1 or 2 bytes prepare controller
-	 * to NACK last byte. Do this before read of dummy data so
+	 * to NACK last byte. Do this before read of extra data so
 	 * controller is setup to NACK last byte.
 	 */
 	cdata[ctrl].flags |= (1ul << 8);
diff --git a/chip/mchp/qmspi.c b/chip/mchp/qmspi.c
index 1a5f9576b8..72eaa91d37 100644
--- a/chip/mchp/qmspi.c
+++ b/chip/mchp/qmspi.c
@@ -436,7 +436,7 @@ uint8_t qmspi_xfr(const struct spi_device_t *spi_device,
  * aligned >= 4 bytes and the number of bytes is a multiple of 4.
  * NOTE on SPI flash commands:
  * This routine does NOT handle SPI flash commands requiring
- * dummy clocks or special mode bytes. Dummy clocks and special mode
+ * extra clocks or special mode bytes. Extra clocks and special mode
  * bytes require additional descriptors. For example the flash read
  * dual command (0x3B):
  * 1. First descriptor transmits 4 bytes (opcode + 24-bit address) on
@@ -444,7 +444,7 @@ uint8_t qmspi_xfr(const struct spi_device_t *spi_device,
  * 2. Second descriptor set for 2 IO pins, 2 bytes, TX disabled. When
  *    this descriptor is executed QMSPI will tri-state IO0 & IO1 and
  *    output 8 clocks (dual mode 4 clocks per byte). The SPI flash may
- *    turn on its output drivers on the first dummy clock.
+ *    turn on its output drivers on the first clock.
  * 3. Third descriptor set for 2 IO pins, read data using DMA. Unit
  *    size and DMA unit size based on number of bytes to read and
  *    alignment of destination buffer.
@@ -455,14 +455,14 @@ uint8_t qmspi_xfr(const struct spi_device_t *spi_device,
  * the SPI flash that changes the default 24-bit address command to
  * require a 32-bit address.
  * 0x03 is 1-1-1
- * 0x3B is 1-1-2 with 8 dummy clocks
- * 0x6B is 1-1-4 with 8 dummy clocks
- * 0xBB is 1-2-2 with 4 dummy clocks
+ * 0x3B is 1-1-2 with 8 clocks
+ * 0x6B is 1-1-4 with 8 clocks
+ * 0xBB is 1-2-2 with 4 clocks
  * Number of IO pins for command
  * Number of IO pins for address
  * Number of IO pins for data
  * Number of bit/bytes for address (3 or 4)
- * Number of dummy clocks after address phase
+ * Number of clocks after address phase
  */
 #ifdef CONFIG_MCHP_QMSPI_TX_DMA
 int qmspi_transaction_async(const struct spi_device_t *spi_device,
@@ -671,7 +671,7 @@ int qmspi_transaction_flush(const struct spi_device_t *spi_device)
  */
 int qmspi_enable(int hw_port, int enable)
 {
-	uint8_t dummy __attribute__((unused)) = 0;
+	uint8_t unused __attribute__((unused)) = 0;
 
 	trace2(0, QMSPI, 0, "qmspi_enable: port = %d enable = %d",
 			hw_port, enable);
@@ -684,13 +684,13 @@ int qmspi_enable(int hw_port, int enable)
 	if (enable) {
 		MCHP_PCR_SLP_DIS_DEV(MCHP_PCR_QMSPI);
 		MCHP_QMSPI0_MODE_ACT_SRST = MCHP_QMSPI_M_SOFT_RESET;
-		dummy = MCHP_QMSPI0_MODE_ACT_SRST;
+		unused = MCHP_QMSPI0_MODE_ACT_SRST;
 		MCHP_QMSPI0_MODE = (MCHP_QMSPI_M_ACTIVATE +
 				MCHP_QMSPI_M_SPI_MODE0 +
 				MCHP_QMSPI_M_CLKDIV_12M);
 	} else {
 		MCHP_QMSPI0_MODE_ACT_SRST = MCHP_QMSPI_M_SOFT_RESET;
-		dummy = MCHP_QMSPI0_MODE_ACT_SRST;
+		unused = MCHP_QMSPI0_MODE_ACT_SRST;
 		MCHP_QMSPI0_MODE_ACT_SRST = 0;
 		MCHP_PCR_SLP_EN_DEV(MCHP_PCR_QMSPI);
 	}
diff --git a/chip/mchp/registers.h b/chip/mchp/registers.h
index f7ef36e68c..145e61257d 100644
--- a/chip/mchp/registers.h
+++ b/chip/mchp/registers.h
@@ -594,7 +594,7 @@
 /* MCHP implements 6 GPIO ports */
 #define MCHP_GPIO_MAX_PORT	(7)
 
-#define DUMMY_GPIO_BANK 0
+#define UNIMPLEMENTED_GPIO_BANK 0
 
 /*
  * MEC1701 documentation GPIO numbers are octal, each control
diff --git a/chip/mchp/util/pack_ec.py b/chip/mchp/util/pack_ec.py
index 22a147ed95..4917deee5d 100755
--- a/chip/mchp/util/pack_ec.py
+++ b/chip/mchp/util/pack_ec.py
@@ -31,10 +31,10 @@ SPI_READ_CMD_LIST = [0x3, 0xb, 0x3b, 0x6b]
 CRC_TABLE = [0x00, 0x07, 0x0e, 0x09, 0x1c, 0x1b, 0x12, 0x15,
              0x38, 0x3f, 0x36, 0x31, 0x24, 0x23, 0x2a, 0x2d]
 
-def dummy_print(*args, **kwargs):
+def mock_print(*args, **kwargs):
   pass
 
-debug_print = dummy_print
+debug_print = mock_print
 
 def Crc8(crc, data):
   """Update CRC8 value."""
diff --git a/chip/mec1322/i2c.c b/chip/mec1322/i2c.c
index fe72b870ef..69344d8390 100644
--- a/chip/mec1322/i2c.c
+++ b/chip/mec1322/i2c.c
@@ -348,7 +348,7 @@ int chip_i2c_xfer(const int port,
 			cdata[controller].transaction_state =
 				I2C_TRANSACTION_OPEN;
 
-			/* Skip over the dummy byte */
+			/* Skip over the unused byte */
 			skip = 1;
 			in_size++;
 		}
@@ -388,7 +388,7 @@ int chip_i2c_xfer(const int port,
 			/*
 			 * We need to know our stop point two bytes in
 			 * advance. If we don't know soon enough, we need
-			 * to do an extra dummy read (to last_addr + 1) to
+			 * to do an extra read (to last_addr + 1) to
 			 * issue the stop.
 			 */
 			push_in_buf(&in, MEC1322_I2C_DATA(controller),
diff --git a/chip/mec1322/lpc.c b/chip/mec1322/lpc.c
index 69fe3b856c..020cd0e23e 100644
--- a/chip/mec1322/lpc.c
+++ b/chip/mec1322/lpc.c
@@ -454,9 +454,9 @@ void lpc_keyboard_put_char(uint8_t chr, int send_irq)
 
 void lpc_keyboard_clear_buffer(void)
 {
-	volatile char dummy __attribute__((unused));
+	volatile char unused __attribute__((unused));
 
-	dummy = MEC1322_8042_OBF_CLR;
+	unused = MEC1322_8042_OBF_CLR;
 }
 
 void lpc_keyboard_resume_irq(void)
diff --git a/chip/mec1322/registers.h b/chip/mec1322/registers.h
index 7e5bbc7cea..c59b590ef8 100644
--- a/chip/mec1322/registers.h
+++ b/chip/mec1322/registers.h
@@ -118,7 +118,7 @@ static inline uintptr_t gpio_port_base(int port_id)
 }
 #define MEC1322_GPIO_CTL(port, id) REG32(gpio_port_base(port) + (id << 2))
 
-#define DUMMY_GPIO_BANK 0
+#define UNIMPLEMENTED_GPIO_BANK 0
 
 
 /* Timer */
diff --git a/chip/mec1322/spi.c b/chip/mec1322/spi.c
index 834fbd10b1..ba58bfb0bd 100644
--- a/chip/mec1322/spi.c
+++ b/chip/mec1322/spi.c
@@ -60,14 +60,14 @@ static int spi_tx(const int port, const uint8_t *txdata, int txlen)
 {
 	int i;
 	int ret = EC_SUCCESS;
-	uint8_t dummy __attribute__((unused)) = 0;
+	uint8_t unused __attribute__((unused)) = 0;
 
 	for (i = 0; i < txlen; ++i) {
 		MEC1322_SPI_TD(port) = txdata[i];
 		ret = wait_byte(port);
 		if (ret != EC_SUCCESS)
 			return ret;
-		dummy = MEC1322_SPI_RD(port);
+		unused = MEC1322_SPI_RD(port);
 	}
 
 	return ret;
@@ -103,7 +103,7 @@ int spi_transaction_flush(const struct spi_device_t *spi_device)
 {
 	int port = spi_device->port;
 	int ret = dma_wait(SPI_DMA_CHANNEL(port));
-	uint8_t dummy __attribute__((unused)) = 0;
+	uint8_t unused __attribute__((unused)) = 0;
 
 	timestamp_t deadline;
 
@@ -121,7 +121,7 @@ int spi_transaction_flush(const struct spi_device_t *spi_device)
 	dma_disable(SPI_DMA_CHANNEL(port));
 	dma_clear_isr(SPI_DMA_CHANNEL(port));
 	if (MEC1322_SPI_SR(port) & 0x2)
-		dummy = MEC1322_SPI_RD(port);
+		unused = MEC1322_SPI_RD(port);
 
 	gpio_set_level(spi_device->gpio_cs, 1);
 
diff --git a/chip/mt8192_scp/ipi_chip.h b/chip/mt8192_scp/ipi_chip.h
index 13345fc6e2..8cc3376880 100644
--- a/chip/mt8192_scp/ipi_chip.h
+++ b/chip/mt8192_scp/ipi_chip.h
@@ -79,8 +79,8 @@ extern int *const ipi_wakeup_table[];
  */
 #define DECLARE_IPI(_id, handler, is_wakeup_src) \
 	struct ipi_num_check##_id { \
-		int dummy1[_id < IPI_COUNT ? 1 : -1]; \
-		int dummy2[is_wakeup_src == 0 || is_wakeup_src == 1 ? 1 : -1]; \
+		int tmp1[_id < IPI_COUNT ? 1 : -1]; \
+		int tmp2[is_wakeup_src == 0 || is_wakeup_src == 1 ? 1 : -1]; \
 	};  \
 	void __keep IPI_HANDLER(_id)(int32_t id, void *buf, uint32_t len) \
 	{ \
diff --git a/chip/mt8192_scp/registers.h b/chip/mt8192_scp/registers.h
index dbf0aed64d..b5c658f534 100644
--- a/chip/mt8192_scp/registers.h
+++ b/chip/mt8192_scp/registers.h
@@ -11,7 +11,7 @@
 #include "common.h"
 #include "compile_time_macros.h"
 
-#define DUMMY_GPIO_BANK 0
+#define UNIMPLEMENTED_GPIO_BANK 0
 
 #define SCP_REG_BASE			0x70000000
 
diff --git a/chip/mt_scp/ipi_chip.h b/chip/mt_scp/ipi_chip.h
index 6b9580e112..867a84c9f8 100644
--- a/chip/mt_scp/ipi_chip.h
+++ b/chip/mt_scp/ipi_chip.h
@@ -104,8 +104,8 @@ extern int *ipi_wakeup_table[];
  */
 #define DECLARE_IPI(_id, handler, is_wakeup_src) \
 	struct ipi_num_check##_id { \
-		int dummy1[_id < IPI_COUNT ? 1 : -1]; \
-		int dummy2[is_wakeup_src == 0 || is_wakeup_src == 1 ? 1 : -1]; \
+		int tmp1[_id < IPI_COUNT ? 1 : -1]; \
+		int tmp2[is_wakeup_src == 0 || is_wakeup_src == 1 ? 1 : -1]; \
 	};  \
 	void __keep IPI_HANDLER(_id)(int32_t id, void *buf, uint32_t len) \
 	{ \
diff --git a/chip/mt_scp/memmap.c b/chip/mt_scp/memmap.c
index 5926ae791e..6d8f2b0c87 100644
--- a/chip/mt_scp/memmap.c
+++ b/chip/mt_scp/memmap.c
@@ -70,7 +70,7 @@ void cpu_invalidate_dcache(void)
 	SCP_CACHE_OP(CACHE_DCACHE) &= ~SCP_CACHE_OP_OP_MASK;
 	SCP_CACHE_OP(CACHE_DCACHE) |=
 		OP_INVALIDATE_ALL_LINES | SCP_CACHE_OP_EN;
-	/* Dummy read is necessary to confirm the invalidation finish. */
+	/* Read is necessary to confirm the invalidation finish. */
 	REG32(CACHE_TRANS_SCP_CACHE_ADDR);
 	asm volatile("dsb;");
 }
@@ -85,7 +85,7 @@ void cpu_invalidate_dcache_range(uintptr_t base, unsigned int length)
 		SCP_CACHE_OP(CACHE_DCACHE) = addr & SCP_CACHE_OP_TADDR_MASK;
 		SCP_CACHE_OP(CACHE_DCACHE) |=
 			OP_INVALIDATE_ONE_LINE_BY_ADDRESS | SCP_CACHE_OP_EN;
-		/* Dummy read necessary to confirm the invalidation finish. */
+		/* Read necessary to confirm the invalidation finish. */
 		REG32(addr);
 	}
 	asm volatile("dsb;");
@@ -99,7 +99,7 @@ void cpu_clean_invalidate_dcache(void)
 	SCP_CACHE_OP(CACHE_DCACHE) &= ~SCP_CACHE_OP_OP_MASK;
 	SCP_CACHE_OP(CACHE_DCACHE) |=
 		OP_INVALIDATE_ALL_LINES | SCP_CACHE_OP_EN;
-	/* Dummy read necessary to confirm the invalidation finish. */
+	/* Read necessary to confirm the invalidation finish. */
 	REG32(CACHE_TRANS_SCP_CACHE_ADDR);
 	asm volatile("dsb;");
 }
@@ -117,7 +117,7 @@ void cpu_clean_invalidate_dcache_range(uintptr_t base, unsigned int length)
 		SCP_CACHE_OP(CACHE_DCACHE) = addr & SCP_CACHE_OP_TADDR_MASK;
 		SCP_CACHE_OP(CACHE_DCACHE) |=
 			OP_INVALIDATE_ONE_LINE_BY_ADDRESS | SCP_CACHE_OP_EN;
-		/* Dummy read necessary to confirm the invalidation finish. */
+		/* Read necessary to confirm the invalidation finish. */
 		REG32(addr);
 	}
 	asm volatile("dsb;");
diff --git a/chip/mt_scp/registers.h b/chip/mt_scp/registers.h
index bce632c6b7..21270b452d 100644
--- a/chip/mt_scp/registers.h
+++ b/chip/mt_scp/registers.h
@@ -573,7 +573,7 @@
  */
 #define AP_GPIO_MODE(n)			REG32(AP_GPIO_BASE + 0x300 + ((n) << 4))
 #define AP_GPIO_TRAP			REG32(AP_GPIO_BASE + 0x6B0)
-#define AP_GPIO_DUMMY			REG32(AP_GPIO_BASE + 0x6C0)
+#define AP_GPIO_UNIMPLEMENTED		REG32(AP_GPIO_BASE + 0x6C0)
 #define AP_GPIO_DBG			REG32(AP_GPIO_BASE + 0x6D0)
 #define AP_GPIO_BANK			REG32(AP_GPIO_BASE + 0x6E0)
 /* AP_GPIO_SEC, n in [0..5] */
@@ -610,7 +610,7 @@
 #define OSC_MOD_MASK			(0x03 << 0)
 #define OSC_DIV2_EN			BIT(2)
 
-#define DUMMY_GPIO_BANK 0
+#define UNIMPLEMENTED_GPIO_BANK 0
 
 #ifndef __ASSEMBLER__
 
diff --git a/chip/npcx/i2c.c b/chip/npcx/i2c.c
index 17b183bc71..b4879081e8 100644
--- a/chip/npcx/i2c.c
+++ b/chip/npcx/i2c.c
@@ -99,7 +99,7 @@ enum smb_oper_state_t {
 	SMB_MASTER_START,
 	SMB_WRITE_OPER,
 	SMB_READ_OPER,
-	SMB_DUMMY_READ_OPER,
+	SMB_FAKE_READ_OPER,
 	SMB_REPEAT_START,
 	SMB_WRITE_SUSPEND,
 	SMB_READ_SUSPEND,
@@ -348,7 +348,7 @@ enum smb_error i2c_master_transaction(int controller)
 	} else if (p_status->oper_state == SMB_READ_SUSPEND) {
 		if (!IS_ENABLED(NPCX_I2C_FIFO_SUPPORT)) {
 			/*
-			 * Do dummy read if read length is 1 and I2C_XFER_STOP
+			 * Do extra read if read length is 1 and I2C_XFER_STOP
 			 * is set simultaneously.
 			 */
 			if (p_status->sz_rxbuf == 1 &&
@@ -356,13 +356,13 @@ enum smb_error i2c_master_transaction(int controller)
 				/*
 				 * Since SCL is released after reading last
 				 * byte from previous transaction, adding a
-				 * dummy byte for next transaction which let
+				 * extra byte for next transaction which let
 				 * ec sets NACK bit in time is necessary.
 				 * Or i2c master cannot generate STOP
 				 * when the last byte is ACK during receiving.
 				 */
 				p_status->sz_rxbuf++;
-				p_status->oper_state = SMB_DUMMY_READ_OPER;
+				p_status->oper_state = SMB_FAKE_READ_OPER;
 			} else
 				/*
 				 * Need to read the other bytes from
@@ -475,7 +475,7 @@ void i2c_done(int controller)
 			NPCX_SMBFIF_CTS(controller) =
 						BIT(NPCX_SMBFIF_CTS_RXF_TXE);
 
-		/* Clear SDAST by writing dummy byte */
+		/* Clear SDAST by writing mock byte */
 		I2C_WRITE_BYTE(controller, 0xFF);
 	}
 
@@ -536,8 +536,8 @@ static void i2c_handle_receive(int controller)
 	I2C_READ_BYTE(controller, data);
 	CPRINTS("-R(%02x)", data);
 
-	/* Read to buf. Skip last byte if meet SMB_DUMMY_READ_OPER */
-	if (p_status->oper_state == SMB_DUMMY_READ_OPER &&
+	/* Read to buf. Skip last byte if meet SMB_FAKE_READ_OPER */
+	if (p_status->oper_state == SMB_FAKE_READ_OPER &&
 			p_status->idx_buf == (p_status->sz_rxbuf - 1))
 		p_status->idx_buf++;
 	else
@@ -735,7 +735,7 @@ static void i2c_handle_sda_irq(int controller)
 	}
 	/* 3 Handle master read operation (read or after a write operation) */
 	else if (p_status->oper_state == SMB_READ_OPER ||
-			p_status->oper_state == SMB_DUMMY_READ_OPER) {
+			p_status->oper_state == SMB_FAKE_READ_OPER) {
 		if (IS_ENABLED(NPCX_I2C_FIFO_SUPPORT))
 			i2c_fifo_handle_receive(controller);
 		else
@@ -755,7 +755,7 @@ void i2c_master_int_handler (int controller)
 		CPUTS("-SP");
 		/* Clear BER Bit */
 		SET_BIT(NPCX_SMBST(controller), NPCX_SMBST_BER);
-		/* Mask sure slave doesn't hold bus by dummy reading */
+		/* Make sure slave doesn't hold bus by reading */
 		I2C_READ_BYTE(controller, data);
 
 		/* Set error code */
diff --git a/chip/npcx/registers.h b/chip/npcx/registers.h
index 8e94f1f125..5b173493d6 100644
--- a/chip/npcx/registers.h
+++ b/chip/npcx/registers.h
@@ -509,7 +509,7 @@ enum {
 #define GPIO_D GPIO_PORT_D
 #define GPIO_E GPIO_PORT_E
 #define GPIO_F GPIO_PORT_F
-#define DUMMY_GPIO_BANK GPIO_PORT_0
+#define UNIMPLEMENTED_GPIO_BANK GPIO_PORT_0
 
 /******************************************************************************/
 /* MSWC Registers */
diff --git a/chip/npcx/spi.c b/chip/npcx/spi.c
index 3be5f16410..6ac8fe1b9e 100644
--- a/chip/npcx/spi.c
+++ b/chip/npcx/spi.c
@@ -35,9 +35,9 @@
  */
 static void clear_databuf(void)
 {
-	volatile uint8_t dummy __attribute__((unused));
+	volatile uint8_t unused __attribute__((unused));
 	while (IS_BIT_SET(NPCX_SPI_STAT, NPCX_SPI_STAT_RBF))
-		dummy = NPCX_SPI_DATA;
+		unused = NPCX_SPI_DATA;
 }
 
 /**
@@ -156,7 +156,7 @@ int spi_transaction(const struct spi_device_t *spi_device,
 		/* Waiting till reading is finished */
 		while (!IS_BIT_SET(NPCX_SPI_STAT, NPCX_SPI_STAT_RBF))
 			;
-		/* Reading the (dummy) data */
+		/* Reading the (unused) data */
 		clear_databuf();
 	}
 	CPRINTS("write end");
@@ -165,7 +165,7 @@ int spi_transaction(const struct spi_device_t *spi_device,
 		/* Making sure we can write */
 		while (IS_BIT_SET(NPCX_SPI_STAT, NPCX_SPI_STAT_BSY))
 			;
-		/* Write the (dummy) data */
+		/* Write the (unused) data */
 		NPCX_SPI_DATA =  0;
 		/* Wait till reading is finished */
 		while (!IS_BIT_SET(NPCX_SPI_STAT, NPCX_SPI_STAT_RBF))
diff --git a/chip/nrf51/registers.h b/chip/nrf51/registers.h
index d41e80c76c..daf014df72 100644
--- a/chip/nrf51/registers.h
+++ b/chip/nrf51/registers.h
@@ -665,7 +665,7 @@
 #define NRF51_PIN_CNF_SENSE_HIGH       (2<<16)
 #define NRF51_PIN_CNF_SENSE_LOW        (3<<16)
 
-#define DUMMY_GPIO_BANK     GPIO_0  /* for UNIMPLEMENTED() macro */
+#define UNIMPLEMENTED_GPIO_BANK     GPIO_0  /* for UNIMPLEMENTED() macro */
 
 #define NRF51_PPI_BASE                 0x4001F000
 #define NRF51_PPI_CHEN                 REG32(NRF51_PPI_BASE + 0x500)
diff --git a/chip/stm32/adc-stm32f3.c b/chip/stm32/adc-stm32f3.c
index 180dc05c3b..fb3e4604a8 100644
--- a/chip/stm32/adc-stm32f3.c
+++ b/chip/stm32/adc-stm32f3.c
@@ -231,7 +231,7 @@ static void adc_init(void)
 
 	/*
 	 * ADC clock is divided with respect to AHB, so no delay needed
-	 * here. If ADC clock is the same as AHB, a dummy read on ADC
+	 * here. If ADC clock is the same as AHB, a read on ADC
 	 * register is needed here.
 	 */
 
diff --git a/chip/stm32/clock-stm32f0.c b/chip/stm32/clock-stm32f0.c
index bea8a7b829..8cfbaef111 100644
--- a/chip/stm32/clock-stm32f0.c
+++ b/chip/stm32/clock-stm32f0.c
@@ -388,14 +388,14 @@ int clock_get_freq(void)
 
 void clock_wait_bus_cycles(enum bus_type bus, uint32_t cycles)
 {
-	volatile uint32_t dummy __attribute__((unused));
+	volatile uint32_t unused __attribute__((unused));
 
 	if (bus == BUS_AHB) {
 		while (cycles--)
-			dummy = STM32_DMA1_REGS->isr;
+			unused = STM32_DMA1_REGS->isr;
 	} else { /* APB */
 		while (cycles--)
-			dummy = STM32_USART_BRR(STM32_USART1_BASE);
+			unused = STM32_USART_BRR(STM32_USART1_BASE);
 	}
 }
 
diff --git a/chip/stm32/clock-stm32f4.c b/chip/stm32/clock-stm32f4.c
index 709ac42981..7b83b8507e 100644
--- a/chip/stm32/clock-stm32f4.c
+++ b/chip/stm32/clock-stm32f4.c
@@ -174,14 +174,14 @@ int clock_get_freq(void)
 
 void clock_wait_bus_cycles(enum bus_type bus, uint32_t cycles)
 {
-	volatile uint32_t dummy __attribute__((unused));
+	volatile uint32_t unused __attribute__((unused));
 
 	if (bus == BUS_AHB) {
 		while (cycles--)
-			dummy = STM32_DMA_GET_ISR(0);
+			unused = STM32_DMA_GET_ISR(0);
 	} else { /* APB */
 		while (cycles--)
-			dummy = STM32_USART_BRR(STM32_USART1_BASE);
+			unused = STM32_USART_BRR(STM32_USART1_BASE);
 	}
 }
 
diff --git a/chip/stm32/clock-stm32g4.c b/chip/stm32/clock-stm32g4.c
index 488adacf59..4a91e1ad42 100644
--- a/chip/stm32/clock-stm32g4.c
+++ b/chip/stm32/clock-stm32g4.c
@@ -229,14 +229,14 @@ int clock_get_freq(void)
 
 void clock_wait_bus_cycles(enum bus_type bus, uint32_t cycles)
 {
-	volatile uint32_t dummy __attribute__((unused));
+	volatile uint32_t unused __attribute__((unused));
 
 	if (bus == BUS_AHB) {
 		while (cycles--)
-			dummy = STM32_DMA1_REGS->isr;
+			unused = STM32_DMA1_REGS->isr;
 	} else { /* APB */
 		while (cycles--)
-			dummy = STM32_USART_BRR(STM32_USART1_BASE);
+			unused = STM32_USART_BRR(STM32_USART1_BASE);
 	}
 }
 
diff --git a/chip/stm32/clock-stm32h7.c b/chip/stm32/clock-stm32h7.c
index bfc56f81df..ba233dbd76 100644
--- a/chip/stm32/clock-stm32h7.c
+++ b/chip/stm32/clock-stm32h7.c
@@ -104,14 +104,14 @@ int clock_get_timer_freq(void)
 
 void clock_wait_bus_cycles(enum bus_type bus, uint32_t cycles)
 {
-	volatile uint32_t dummy __attribute__((unused));
+	volatile uint32_t unused __attribute__((unused));
 
 	if (bus == BUS_AHB) {
 		while (cycles--)
-			dummy = STM32_GPIO_IDR(GPIO_A);
+			unused = STM32_GPIO_IDR(GPIO_A);
 	} else { /* APB */
 		while (cycles--)
-			dummy = STM32_USART_BRR(STM32_USART1_BASE);
+			unused = STM32_USART_BRR(STM32_USART1_BASE);
 	}
 }
 
diff --git a/chip/stm32/clock-stm32l.c b/chip/stm32/clock-stm32l.c
index 96acfc85ad..a4e9dd7cdf 100644
--- a/chip/stm32/clock-stm32l.c
+++ b/chip/stm32/clock-stm32l.c
@@ -57,14 +57,14 @@ int clock_get_timer_freq(void)
 
 void clock_wait_bus_cycles(enum bus_type bus, uint32_t cycles)
 {
-	volatile uint32_t dummy __attribute__((unused));
+	volatile uint32_t unused __attribute__((unused));
 
 	if (bus == BUS_AHB) {
 		while (cycles--)
-			dummy = STM32_DMA1_REGS->isr;
+			unused = STM32_DMA1_REGS->isr;
 	} else { /* APB */
 		while (cycles--)
-			dummy = STM32_USART_BRR(STM32_USART1_BASE);
+			unused = STM32_USART_BRR(STM32_USART1_BASE);
 	}
 }
 
diff --git a/chip/stm32/clock-stm32l4.c b/chip/stm32/clock-stm32l4.c
index b180177d0b..1bba787779 100644
--- a/chip/stm32/clock-stm32l4.c
+++ b/chip/stm32/clock-stm32l4.c
@@ -44,14 +44,14 @@ int clock_get_timer_freq(void)
 
 void clock_wait_bus_cycles(enum bus_type bus, uint32_t cycles)
 {
-	volatile uint32_t dummy __attribute__((unused));
+	volatile uint32_t unused __attribute__((unused));
 
 	if (bus == BUS_AHB) {
 		while (cycles--)
-			dummy = STM32_DMA1_REGS->isr;
+			unused = STM32_DMA1_REGS->isr;
 	} else { /* APB */
 		while (cycles--)
-			dummy = STM32_USART_BRR(STM32_USART1_BASE);
+			unused = STM32_USART_BRR(STM32_USART1_BASE);
 	}
 }
 
diff --git a/chip/stm32/i2c-stm32f4.c b/chip/stm32/i2c-stm32f4.c
index 8c08395edd..515aed20eb 100644
--- a/chip/stm32/i2c-stm32f4.c
+++ b/chip/stm32/i2c-stm32f4.c
@@ -860,7 +860,7 @@ static void i2c_event_handler(int port)
 	static int rx_pending, buf_idx;
 	static uint16_t addr_8bit;
 
-	volatile uint32_t dummy __attribute__((unused));
+	volatile uint32_t unused __attribute__((unused));
 
 	i2c_cr1 = STM32_I2C_CR1(port);
 	i2c_sr2 = STM32_I2C_SR2(port);
@@ -903,8 +903,8 @@ static void i2c_event_handler(int port)
 		/* Enable buffer interrupt to start receive/response */
 		STM32_I2C_CR2(port) |= STM32_I2C_CR2_ITBUFEN;
 		/* Clear ADDR bit */
-		dummy = STM32_I2C_SR1(port);
-		dummy = STM32_I2C_SR2(port);
+		unused = STM32_I2C_SR1(port);
+		unused = STM32_I2C_SR2(port);
 		/* Inhibit stop mode when addressed until STOPF flag is set */
 		disable_sleep(SLEEP_MASK_I2C_SLAVE);
 	}
@@ -964,7 +964,7 @@ static void i2c_event_handler(int port)
 		/* Clear AF */
 		STM32_I2C_SR1(port) &= ~STM32_I2C_SR1_AF;
 		/* Clear STOPF: read SR1 and write CR1 */
-		dummy = STM32_I2C_SR1(port);
+		unused = STM32_I2C_SR1(port);
 		STM32_I2C_CR1(port) = i2c_cr1 | STM32_I2C_CR1_PE;
 
 		/* No longer inhibit deep sleep after stop condition */
diff --git a/chip/stm32/registers.h b/chip/stm32/registers.h
index ea6b2db84a..574921c63e 100644
--- a/chip/stm32/registers.h
+++ b/chip/stm32/registers.h
@@ -183,7 +183,7 @@ typedef volatile struct timer_ctlr timer_ctlr_t;
 #define GPIO_J                       STM32_GPIOJ_BASE
 #define GPIO_K                       STM32_GPIOK_BASE
 
-#define DUMMY_GPIO_BANK GPIO_A
+#define UNIMPLEMENTED_GPIO_BANK GPIO_A
 
 
 /* --- I2C --- */
diff --git a/chip/stm32/spi.c b/chip/stm32/spi.c
index 21857837c2..3dbbbc4fa9 100644
--- a/chip/stm32/spi.c
+++ b/chip/stm32/spi.c
@@ -308,7 +308,7 @@ static void tx_status(uint8_t byte)
 static void setup_for_transaction(void)
 {
 	stm32_spi_regs_t *spi __attribute__((unused)) = STM32_SPI1_REGS;
-	volatile uint8_t dummy __attribute__((unused));
+	volatile uint8_t unused __attribute__((unused));
 
 	/* clear this as soon as possible */
 	setup_transaction_later = 0;
@@ -325,15 +325,15 @@ static void setup_for_transaction(void)
 	dma_disable(STM32_DMAC_SPI1_TX);
 
 	/*
-	 * Read dummy bytes in case there are some pending; this prevents the
+	 * Read unused bytes in case there are some pending; this prevents the
 	 * receive DMA from getting that byte right when we start it.
 	 */
-	dummy = SPI_RXDR;
+	unused = SPI_RXDR;
 #if defined(CHIP_FAMILY_STM32F0) || defined(CHIP_FAMILY_STM32L4)
 	/* 4 Bytes makes sure the RX FIFO on the F0 is empty as well. */
-	dummy = spi->dr;
-	dummy = spi->dr;
-	dummy = spi->dr;
+	unused = spi->dr;
+	unused = spi->dr;
+	unused = spi->dr;
 #endif
 
 	/* Start DMA */
@@ -523,7 +523,7 @@ void spi_event(enum gpio_signal signal)
 		/*
 		 * Check how big the packet should be.  We can't just wait to
 		 * see how much data the host sends, because it will keep
-		 * sending dummy data until we respond.
+		 * sending extra data until we respond.
 		 */
 		pkt_size = host_request_expected_size(r);
 		if (pkt_size == 0 || pkt_size > sizeof(in_msg))
diff --git a/chip/stm32/spi_master.c b/chip/stm32/spi_master.c
index 4b48f8ea80..c2d36bb4d9 100644
--- a/chip/stm32/spi_master.c
+++ b/chip/stm32/spi_master.c
@@ -117,11 +117,11 @@ static int spi_rx_done(stm32_spi_regs_t *spi)
 /* Read until RX FIFO is empty (i.e. RX done) */
 static int spi_clear_rx_fifo(stm32_spi_regs_t *spi)
 {
-	uint8_t dummy __attribute__((unused));
+	uint8_t unused __attribute__((unused));
 	uint32_t start = __hw_clock_source_read(), delta;
 
 	while (!spi_rx_done(spi)) {
-		dummy = spi->dr;  /* Read one byte from FIFO */
+		unused = spi->dr;  /* Read one byte from FIFO */
 		delta = __hw_clock_source_read() - start;
 		if (delta >= SPI_TRANSACTION_TIMEOUT_USEC)
 			return EC_ERROR_TIMEOUT;
diff --git a/chip/stm32/trng.c b/chip/stm32/trng.c
index eff3ca0181..48d5335c53 100644
--- a/chip/stm32/trng.c
+++ b/chip/stm32/trng.c
@@ -21,7 +21,7 @@ uint32_t rand(void)
 	/* Wait for a valid random number */
 	while (!(STM32_RNG_SR & STM32_RNG_SR_DRDY) && --tries)
 		;
-	/* we cannot afford to feed the caller with a dummy number */
+	/* we cannot afford to feed the caller with an arbitrary number */
 	if (!tries)
 		software_panic(PANIC_SW_BAD_RNG, task_get_current());
 	/* Finally the 32-bit of entropy */