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| author | Caveh Jalali <caveh@chromium.org> | 2019-09-30 22:53:53 -0700 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2019-10-08 07:53:03 +0000 |
| commit | 159bc2bccee3ea897d4f89abe2f86d9e8c933815 (patch) | |
| tree | dbbaf42f6802e300d294bebe3d0a0b6ad24d7cad /chip | |
| parent | 4231e6997e4a75764c7d4fc6b96f4cc090ee026c (diff) | |
| download | chrome-ec-159bc2bccee3ea897d4f89abe2f86d9e8c933815.tar.gz | |
npcx7: fix RAM powerdown regression
chromium:1518660 introduced a subtle change in which RAM bank
power-down bits are set. this change reverts to the original bit
pattern and masks the reserved bits as suggested by nuvoton.
BUG=b:141715856
BRANCH=none
TEST=boots on atlas.
Change-Id: Idfbedd73fd46aa639f12c9991911d96f15739174
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1833153
Reviewed-by: Caveh Jalali <caveh@google.com>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Diffstat (limited to 'chip')
| -rw-r--r-- | chip/npcx/system-npcx7.c | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/chip/npcx/system-npcx7.c b/chip/npcx/system-npcx7.c index 9e461c5a1b..1ec719c641 100644 --- a/chip/npcx/system-npcx7.c +++ b/chip/npcx/system-npcx7.c @@ -23,7 +23,8 @@ /* Macros for last 32K ram block */ #define LAST_RAM_BLK ((NPCX_RAM_SIZE / (32 * 1024)) - 1) -#define RAM_PD_MASK (BIT(LAST_RAM_BLK) - 1) +/* Higher bits are reserved and need to be masked */ +#define RAM_PD_MASK (~BIT(LAST_RAM_BLK)) /*****************************************************************************/ /* IC specific low-level driver depends on chip series */ @@ -112,7 +113,7 @@ __enter_hibernate_in_last_block(void) * for better power consumption. */ NPCX_RAM_PD(0) = RAM_PD_MASK & 0xFF; - NPCX_RAM_PD(1) = RAM_PD_MASK >> 8; + NPCX_RAM_PD(1) = (RAM_PD_MASK >> 8) & 0x0F; /* Set deep idle mode */ NPCX_PMCSR = 0x6; |