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| author | Scott Collyer <scollyer@google.com> | 2017-08-21 09:02:48 -0700 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2017-11-15 16:07:26 -0800 |
| commit | 071142fe688c05ef1ffd54057409995f12504c1d (patch) | |
| tree | 7e59643f583ac231ec1dfd7f93e6b85d8235b331 /chip | |
| parent | 6c92b0fcd08d00134f66d879d75a55d1cede5822 (diff) | |
| download | chrome-ec-071142fe688c05ef1ffd54057409995f12504c1d.tar.gz | |
system: Add wait-ext option to ec reboot command
EC_IN_RW signal is used to determine if the switch to dev mode can be
safely made. However, EC_IN_RW needs the EC_RST_L line driven low in
order to be reset. In faft tests that utilize crosEcSoftrecPower
method, EC_RST_L is not being driven by servo to fix other test
failures related to keeping EC and AC reboots in sync.
This CL adds a new argument 'wait-ext' to the EC reboot command.
When this option is used, instead of the EC generating a reset via
it's system watchdog, it will wait 10 seconds for EC_RST_L to be
driven.
BUG=b:64603944
BRANCH=coral
CQ-DEPEND=I086687c3dd7591460099267880d56ab8265d2e4b
TEST=Ran "/usr/bin/test_that --board=coral <ip addr> firmware_DevMode"
mutliple times and verified that it passes. Previoulsy, this test
always fails when the EC is in RW before it starts. Also tested
platform_ServoPowerStateController_USBPluggedin and verified it passed.
Change-Id: I614f9156066d5719601ee43e29c7a064f9bba6e2
Signed-off-by: Scott Collyer <scollyer@google.com>
Reviewed-on: https://chromium-review.googlesource.com/737524
Commit-Ready: Scott Collyer <scollyer@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Diffstat (limited to 'chip')
| -rw-r--r-- | chip/npcx/system.c | 29 |
1 files changed, 15 insertions, 14 deletions
diff --git a/chip/npcx/system.c b/chip/npcx/system.c index 51c7c6e74a..96879b40e4 100644 --- a/chip/npcx/system.c +++ b/chip/npcx/system.c @@ -21,6 +21,7 @@ #include "task.h" #include "timer.h" #include "util.h" +#include "watchdog.h" /* Delay after writing TTC for value to latch */ #define MTC_TTC_LOAD_DELAY_US 250 @@ -702,28 +703,28 @@ void system_pre_init(void) void system_reset(int flags) { - uint32_t save_flags = 0; + uint32_t save_flags; /* Disable interrupts to avoid task swaps during reboot */ interrupt_disable(); - /* Save current reset reasons if necessary */ - if (flags & SYSTEM_RESET_PRESERVE_FLAGS) - save_flags = system_get_reset_flags() | RESET_FLAG_PRESERVED; - - /* Add in AP off flag into saved flags. */ - if (flags & SYSTEM_RESET_LEAVE_AP_OFF) - save_flags |= RESET_FLAG_AP_OFF; - - /* Save reset flag */ - if (flags & SYSTEM_RESET_HARD) - save_flags |= RESET_FLAG_HARD; - else - save_flags |= RESET_FLAG_SOFT; + /* Get flags to be saved in BBRAM */ + system_encode_save_flags(flags, &save_flags); /* Store flags to battery backed RAM. */ chip_save_reset_flags(save_flags); + /* If WAIT_EXT is set, then allow 10 seconds for external reset */ + if (flags & SYSTEM_RESET_WAIT_EXT) { + int i; + + /* Wait 10 seconds for external reset */ + for (i = 0; i < 1000; i++) { + watchdog_reload(); + udelay(10000); + } + } + /* Ask the watchdog to trigger a hard reboot */ system_watchdog_reset(); |