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| author | Nicolas Boichat <drinkcat@chromium.org> | 2018-10-22 16:56:10 +0800 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2018-10-29 04:15:05 -0700 |
| commit | 51a6070f845ed670c5a198a7045af3d3bb3bbdd4 (patch) | |
| tree | a247c66e5299aae1d9a657fdd695c3759063ec40 /chip | |
| parent | 149190dd3a823d835be71ec4b4e4ae9e5120c774 (diff) | |
| download | chrome-ec-51a6070f845ed670c5a198a7045af3d3bb3bbdd4.tar.gz | |
system: Remember if reset was due to AP watchdog triggering
On MT8183, when EC detects a watchdog reset, EC needs to reboot
itself in preparation for the next boot. This means that AP loses
the reset cause (as AP system reset is toggled), and, therefore,
we need to save the reset reason in the EC.
BRANCH=none
BUG=b:109900671
TEST=apshutdown, powerb, see that reset reason is: reset-pin
TEST=Use test-wd from bug. Reset reason: reset-pin ap-watchdog
Change-Id: I2e30306db5727a22de930f00dc30de40b9695bef
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1295890
Reviewed-by: Jett Rink <jettrink@chromium.org>
Diffstat (limited to 'chip')
| -rw-r--r-- | chip/stm32/system.c | 32 |
1 files changed, 32 insertions, 0 deletions
diff --git a/chip/stm32/system.c b/chip/stm32/system.c index a03550d7f9..c7ff4f23d9 100644 --- a/chip/stm32/system.c +++ b/chip/stm32/system.c @@ -33,9 +33,26 @@ /* We use 16-bit BKP / BBRAM entries. */ #define STM32_BKP_ENTRIES (STM32_BKP_BYTES / 2) +/* + * Use 32-bit for reset flags, if we have space for it: + * - 2 indexes are used unconditionally (SCRATCHPAD and SAVED_RESET_FLAGS) + * - VBNV_CONTEXT requires 8 indexes, so a total of 10 (which is the total + * number of entries on some STM32 variants). + * - Other config options are not a problem (they only take a few entries) + * + * Given this, we can only add an extra entry for the top 16-bit of reset flags + * if VBNV_CONTEXT is not enabled, or if we have more than 10 entries. + */ +#if !defined(CONFIG_HOSTCMD_VBNV_CONTEXT) || STM32_BKP_ENTRIES > 10 +#define CONFIG_STM32_RESET_FLAGS_EXTENDED +#endif + enum bkpdata_index { BKPDATA_INDEX_SCRATCHPAD, /* General-purpose scratchpad */ BKPDATA_INDEX_SAVED_RESET_FLAGS, /* Saved reset flags */ +#ifdef CONFIG_STM32_RESET_FLAGS_EXTENDED + BKPDATA_INDEX_SAVED_RESET_FLAGS_2, /* Saved reset flags (cont) */ +#endif #ifdef CONFIG_HOSTCMD_VBNV_CONTEXT BKPDATA_INDEX_VBNV_CONTEXT0, BKPDATA_INDEX_VBNV_CONTEXT1, @@ -152,12 +169,19 @@ static void check_reset_cause(void) uint32_t raw_cause = STM32_RCC_RESET_CAUSE; uint32_t pwr_status = STM32_PWR_RESET_CAUSE; +#ifdef CONFIG_STM32_RESET_FLAGS_EXTENDED + flags |= bkpdata_read(BKPDATA_INDEX_SAVED_RESET_FLAGS_2) << 16; +#endif + /* Clear the hardware reset cause by setting the RMVF bit */ STM32_RCC_RESET_CAUSE |= RESET_CAUSE_RMVF; /* Clear SBF in PWR_CSR */ STM32_PWR_RESET_CAUSE_CLR |= RESET_CAUSE_SBF_CLR; /* Clear saved reset flags */ bkpdata_write(BKPDATA_INDEX_SAVED_RESET_FLAGS, 0); +#ifdef CONFIG_STM32_RESET_FLAGS_EXTENDED + bkpdata_write(BKPDATA_INDEX_SAVED_RESET_FLAGS_2, 0); +#endif if (raw_cause & RESET_CAUSE_WDG) { /* @@ -343,9 +367,17 @@ void system_reset(int flags) if (flags & SYSTEM_RESET_HARD) save_flags |= RESET_FLAG_HARD; +#ifdef CONFIG_STM32_RESET_FLAGS_EXTENDED + if (flags & SYSTEM_RESET_AP_WATCHDOG) + save_flags |= RESET_FLAG_AP_WATCHDOG; + + bkpdata_write(BKPDATA_INDEX_SAVED_RESET_FLAGS, save_flags & 0xffff); + bkpdata_write(BKPDATA_INDEX_SAVED_RESET_FLAGS_2, save_flags >> 16); +#else /* Reset flags are 32-bits, but BBRAM entry is only 16 bits. */ ASSERT(!(save_flags >> 16)); bkpdata_write(BKPDATA_INDEX_SAVED_RESET_FLAGS, save_flags); +#endif if (flags & SYSTEM_RESET_HARD) { #ifdef CONFIG_SOFTWARE_PANIC |