diff options
| author | Daisuke Nojiri <dnojiri@chromium.org> | 2018-09-26 12:32:50 -0700 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2018-09-27 19:44:47 -0700 |
| commit | f90282218998398948f3cdcc2f74d0b5fa0ab11e (patch) | |
| tree | b9178301885d04ed76c76f3712e006d8e6e8de4b /chip | |
| parent | f5d7b19436d8e0e33a8d4a1e46215ee119098f1d (diff) | |
| download | chrome-ec-f90282218998398948f3cdcc2f74d0b5fa0ab11e.tar.gz | |
stm32h7: Use high performance voltage scaler before clock up
This patch switches the voltage scaler to VOS1 before increasing
the clock speed (PLL) and switches it back to VOS3 after reducing
the clock speed (HSI).
BUG=b:114520154
BRANCH=none
TEST=Enroll and match fingerprint on Nocturne without exceptions.
Change-Id: Ie369a382bab76efb090ca5fecf2cdb5fd05e0575
Reviewed-on: https://chromium-review.googlesource.com/1246832
Tested-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Commit-Queue: Daisuke Nojiri <dnojiri@chromium.org>
(cherry picked from commit e1f0d3b50bfa30abd2d2aa1a1aee1456bb049662)
Reviewed-on: https://chromium-review.googlesource.com/1249721
Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Diffstat (limited to 'chip')
| -rw-r--r-- | chip/stm32/clock-stm32h7.c | 10 | ||||
| -rw-r--r-- | chip/stm32/registers.h | 5 |
2 files changed, 15 insertions, 0 deletions
diff --git a/chip/stm32/clock-stm32h7.c b/chip/stm32/clock-stm32h7.c index 48915aca09..95d9b1e96c 100644 --- a/chip/stm32/clock-stm32h7.c +++ b/chip/stm32/clock-stm32h7.c @@ -145,6 +145,14 @@ static void clock_switch_osc(enum clock_osc osc) ; } +static void switch_voltage_scale(uint32_t vos) +{ + STM32_PWR_D3CR &= ~STM32_PWR_D3CR_VOSMASK; + STM32_PWR_D3CR |= vos; + while (!(STM32_PWR_D3CR & STM32_PWR_D3CR_VOSRDY)) + ; +} + static void clock_set_osc(enum clock_osc osc) { if (osc == current_osc) @@ -165,9 +173,11 @@ static void clock_set_osc(enum clock_osc osc) clock_flash_latency(FLASH_ACLK_64MHZ); /* Turn off the PLL1 to save power */ STM32_RCC_CR &= ~STM32_RCC_CR_PLL1ON; + switch_voltage_scale(STM32_PWR_D3CR_VOS3); break; case OSC_PLL: + switch_voltage_scale(STM32_PWR_D3CR_VOS1); /* Configure PLL1 using 64 Mhz HSI as input */ STM32_RCC_PLLCKSELR = STM32_RCC_PLLCKSEL_PLLSRC_HSI | STM32_RCC_PLLCKSEL_DIVM1(PLL1_DIVM); diff --git a/chip/stm32/registers.h b/chip/stm32/registers.h index 2a4f1171fc..f01e98dfd7 100644 --- a/chip/stm32/registers.h +++ b/chip/stm32/registers.h @@ -911,6 +911,11 @@ typedef volatile struct timer_ctlr timer_ctlr_t; #define STM32_PWR_CPUCR_CSSF (1 << 9) #define STM32_PWR_CPUCR_RUN_D3 (1 << 11) #define STM32_PWR_D3CR REG32(STM32_PWR_BASE + 0x18) +#define STM32_PWR_D3CR_VOS1 (3 << 14) +#define STM32_PWR_D3CR_VOS2 (2 << 14) +#define STM32_PWR_D3CR_VOS3 (1 << 14) +#define STM32_PWR_D3CR_VOSMASK (3 << 14) +#define STM32_PWR_D3CR_VOSRDY (1 << 13) #define STM32_PWR_WKUPCR REG32(STM32_PWR_BASE + 0x20) #define STM32_PWR_WKUPFR REG32(STM32_PWR_BASE + 0x24) #define STM32_PWR_WKUPEPR REG32(STM32_PWR_BASE + 0x28) |