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| author | Alec Berg <alecaberg@chromium.org> | 2013-10-07 12:23:35 -0700 |
|---|---|---|
| committer | chrome-internal-fetch <chrome-internal-fetch@google.com> | 2014-02-13 16:42:08 +0000 |
| commit | 05725493e46cb00cb90a1a160b7b5fcc7d8abc8c (patch) | |
| tree | d602e28ba4011e511d0e7ccdce959d17bf4b40b2 /common/chipset_haswell.c | |
| parent | 34a506c2594d47ac588299bd3e80cd76d9a58b5d (diff) | |
| download | chrome-ec-05725493e46cb00cb90a1a160b7b5fcc7d8abc8c.tar.gz | |
CHERRY-PICK: lm4: Add a low power idle task.
First implementation of a low power idle task for the LM4 chip. The
low power mode is selected by defining CONFIG_LOW_POWER_IDLE in a
board.h file. This commit turns it on for Peppy, Slippy, and Falco
only because those are the only boards tested.
When using the low power idle task, the chip goes in to deep sleep
when it can. Deep sleep disables clocks to most peripherals and puts
the onboard flash and RAM into a low power mode. The chip is woken
out of deep sleep using the RTC in the hibernate module. Increased
the idle task stack size to handle more involved idle task.
In board.c, the array of GPIO info can be used to select which GPIO
points can wake up the EC from deep sleep. Currenlty selected are
the power button, lid open, AC present, PCH_SLP_S3, and PCH_SLP_S5.
Additionally the port with the KB scan row GPIO point is also
enabled to wake up the EC from deep sleep.
Signed-off-by: Alec Berg <alecaberg@chromium.org>
BUG=chrome-os-partner:25661
BRANCH=none
TEST=Passes all unit tests. Runs on slippy, peppy, and falco with no
noticeable side affects. Verified that the power consumed by the EC
is lower when in S3, S5 and G3 by scoping the sense resistor
powering the chip.
Change-Id: I48112d4ce74fe0a272a1cc3a09e3d1b9b3ce6c25
Original-Change-Id: I83fa9a159a4b79201b99f2c32678dc4fc8921726
Reviewed-on: https://chromium-review.googlesource.com/172183
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Commit-Queue: Alec Berg <alecaberg@chromium.org>
Tested-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/186265
Commit-Queue: Dave Parker <dparker@chromium.org>
Tested-by: Dave Parker <dparker@chromium.org>
Diffstat (limited to 'common/chipset_haswell.c')
| -rw-r--r-- | common/chipset_haswell.c | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/common/chipset_haswell.c b/common/chipset_haswell.c index 9482a860b2..ba4e10991c 100644 --- a/common/chipset_haswell.c +++ b/common/chipset_haswell.c @@ -285,6 +285,12 @@ enum x86_state x86_handle_state(enum x86_state state) /* Call hooks now that rails are up */ hook_notify(HOOK_CHIPSET_RESUME); + /* + * Disable idle task deep sleep. This means that the low + * power idle task will not go into deep sleep while in S0. + */ + disable_sleep(SLEEP_MASK_AP_RUN); + /* Wait 99ms after all voltages good */ msleep(99); @@ -317,6 +323,12 @@ enum x86_state x86_handle_state(enum x86_state state) wireless_enable(0); /* + * Enable idle task deep sleep. Allow the low power idle task + * to go into deep sleep in S3 or lower. + */ + enable_sleep(SLEEP_MASK_AP_RUN); + + /* * Deassert prochot since CPU is off and we're about to drop * +VCCP. */ |