cleanup: Rename geometry constants

Rename and add geometry constants to match spec doc -
https://goo.gl/fnzTvr.

CONFIG_FLASH_BASE becomes CONFIG_PROGRAM_MEMORY_BASE
CONFIG_FLASH_MAPPED becomes CONFIG_MAPPED_STORAGE

Add CONFIG_INTERNAL_STORAGE, CONFIG_EXTERNAL_STORAGE and
CONFIG_MAPPED_STORAGE_BASE where appropriate.

This CL leaves chip/npcx in a broken state -- it's fixed in a follow-up
CL.

BRANCH=None
BUG=chrome-os-partner:23796
TEST=With entire patch series, on both Samus and Glados:
- Verify 'version' EC console command is correct
- Verify 'flashrom -p ec -r read.bin' reads back EC image
- Verify software sync correctly flashes both EC and PD RW images

Change-Id: Idb3c4ed9f7f6edd0a6d49ad11753eba713e67a80
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/297484
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>

1 files changed, 9 insertions, 7 deletions

diff --git a/common/firmware_image.lds.S b/common/firmware_image.lds.S
index d956a3471d..546ad26c63 100644
--- a/common/firmware_image.lds.S
+++ b/common/firmware_image.lds.S
@@ -9,7 +9,7 @@ OUTPUT_FORMAT(BFD_FORMAT, BFD_FORMAT, BFD_FORMAT)
 OUTPUT_ARCH(BFD_ARCH)
 MEMORY
 {
-    FLASH (rx) : ORIGIN = CONFIG_FLASH_BASE, LENGTH = CONFIG_FLASH_SIZE
+    FLASH (rx) : ORIGIN = CONFIG_PROGRAM_MEMORY_BASE, LENGTH = CONFIG_FLASH_SIZE
 }
 SECTIONS
 {
@@ -17,15 +17,16 @@ SECTIONS
 #if defined(NPCX_RO_HEADER)
 /* Replace *_MEM_OFF with *_STORAGE_OFF to indicate flat file contains header
  * or some struture which doesn't belong to FW */
-    .image.RO : AT(CONFIG_FLASH_BASE + CONFIG_RO_STORAGE_OFF) {
+    .image.RO : AT(CONFIG_PROGRAM_MEMORY_BASE + CONFIG_RO_STORAGE_OFF) {
 #else
-    .image.RO : AT(CONFIG_FLASH_BASE + CONFIG_RO_MEM_OFF) {
+    .image.RO : AT(CONFIG_PROGRAM_MEMORY_BASE + CONFIG_RO_MEM_OFF) {
 #endif
         *(.image.RO)
     } > FLASH =0xff
     . = ALIGN(CONFIG_FLASH_BANK_SIZE);
 #ifdef CONFIG_SHAREDLIB
-    .image.libsharedobjs : AT(CONFIG_FLASH_BASE + CONFIG_SHAREDLIB_MEM_OFF) {
+    .image.libsharedobjs : AT(CONFIG_PROGRAM_MEMORY_BASE + \
+                              CONFIG_SHAREDLIB_MEM_OFF) {
         *(.image.libsharedobjs)
     } > FLASH =0xff
     . = ALIGN(CONFIG_FLASH_BANK_SIZE);
@@ -34,13 +35,14 @@ SECTIONS
 /* This is applicable to ECs in which RO and RW execution is
 mapped to the same location but we still have to generate an ec.bin with RO
 and RW images at different Flash offset */
-    .image.RW : AT(CONFIG_FLASH_BASE + CONFIG_RO_MEM_OFF + CONFIG_RO_SIZE) {
+    .image.RW : AT(CONFIG_PROGRAM_MEMORY_BASE + CONFIG_RO_MEM_OFF + \
+                   CONFIG_RO_SIZE) {
 #else
-    .image.RW : AT(CONFIG_FLASH_BASE + CONFIG_RW_MEM_OFF) {
+    .image.RW : AT(CONFIG_PROGRAM_MEMORY_BASE + CONFIG_RW_MEM_OFF) {
 #endif
         *(.image.RW)
     } > FLASH =0xff
-    .padding : AT(CONFIG_FLASH_BASE + CONFIG_FLASH_SIZE - 1) {
+    .padding : AT(CONFIG_PROGRAM_MEMORY_BASE + CONFIG_FLASH_SIZE - 1) {
         BYTE(0xff);
     } > FLASH =0xff
 }