diff options
| author | Mary Ruthven <mruthven@chromium.org> | 2016-05-04 14:33:04 -0700 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2016-06-03 20:14:59 -0700 |
| commit | 6672aa1be1d1eaaefb7fecc0ff697c4ff54dcf8d (patch) | |
| tree | 5618d008492f2b517648baf1aaa26a397fbcd8fc /common/main.c | |
| parent | 767b6152158c0b718e819d6403e2b8e34bd74686 (diff) | |
| download | chrome-ec-6672aa1be1d1eaaefb7fecc0ff697c4ff54dcf8d.tar.gz | |
cr50: enable case closed debug
This change adds a ccd console command to control the usb endpoints.
The uart console command is moved into this command so 'ccd uart
[enable|disable]' controls the AP and EC TX signals instead of the
'uart' console command. CCD can be enabled using 'ccd enable'. This
switches the PHY used by the USB controller to be the external PHY.
Changing the PHY exposes the cr50, AP, and EC consoles as well as the
upgrading mechanisms for the AP, EC and cr50. The AP and EC consoles
will be read only until 'ccd uart enable' is called. Cr50 can be updated
using the usb upgrade endpoint. The EC and AP can be updated using the
USB SPI endpoint.
When CCD is disabled the usb controller will switch to using the AP PHY.
None of the endpoints will be visible to the host.
The USB SPI endpoint can be used to flash the EC or AP using
'flashrom -p raiden_debug_spi:target=[AP|EC]'. If CCD is not enabled
running flashrom using the raiden_debug_spi programmer will fail. Cr50
will not forward the commands to the external AP or EC ROM, so flashrom
will not be able to find the chip.
The UART TX signals are now controlled by the 'ccd uart' console
command instead of the 'uart' console command. The UART TX is enabled
separately from CCD, because we want to be able to enable CCD while
servo is connected, and having the cr50 UART TX pins wired directly to
the Servo TX lines could damage both devices. The AP and EC consoles
are be read only until 'ccd uart enable' is called. 'ccd uart disable'
disconnects the AP and EC TX pins from the UART peripheral.
When RDD becomes reliable on cr50, ccd_set_mode will select the PHY
being used by the g chip USB controller.
BUG=chrome-os-partner:49960,chrome-os-partner:52281
BRANCH=none
TEST=manual
TEST SERVO
power cycle the DUT
connect servo and check that the AP and EC consoles still work
check that both the AP and EC can be flashed using servo.
TEST SUZY Q
Attach Suzy Q
Connect to the all three consoles. Check that the cr50 console
is in read-write mode and the EC and AP consoles are read only.
Attach Servo.
Verify all of the servo functionality described above still
works with suzy q attached and ccd enabled.
Disconnect Servo.
run 'ccd uart enable' on the cr50 console and check both the AP
and EC consoles can be written to.
Check that the AP and EC can be programmed using the
raiden_debug_spi programmer.
Change-Id: I96db2a72fc95086871c9e4c778c19ebd01efb851
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/342563
Diffstat (limited to 'common/main.c')
| -rw-r--r-- | common/main.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/common/main.c b/common/main.c index bafb18c94a..4b537a79da 100644 --- a/common/main.c +++ b/common/main.c @@ -87,7 +87,7 @@ test_mockable __keep int main(void) flash_pre_init(); #endif -#if defined(CONFIG_CASE_CLOSED_DEBUG) +#if defined(CONFIG_CASE_CLOSED_DEBUG) && defined(CONFIG_USB_POWER_DELIVERY) /* * If the device is locked we assert PD_NO_DEBUG, preventing the EC * from interfering with the AP's access to the SPI flash. |