diff options
| author | Shawn Nematbakhsh <shawnn@chromium.org> | 2015-09-04 19:09:33 -0700 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2015-09-16 14:49:31 -0700 |
| commit | d58e54730c03290296df5bb65cb84264e4b2facc (patch) | |
| tree | d736570c84a0e9737b8881ec68b073327a5c2ae5 /common/rwsig.c | |
| parent | 4b3c13ddfefd229dde49fb4cbf5a6bfc49f64973 (diff) | |
| download | chrome-ec-d58e54730c03290296df5bb65cb84264e4b2facc.tar.gz | |
cleanup: Rename geometry constants
Rename and add geometry constants to match spec doc -
https://goo.gl/fnzTvr.
CONFIG_FLASH_BASE becomes CONFIG_PROGRAM_MEMORY_BASE
CONFIG_FLASH_MAPPED becomes CONFIG_MAPPED_STORAGE
Add CONFIG_INTERNAL_STORAGE, CONFIG_EXTERNAL_STORAGE and
CONFIG_MAPPED_STORAGE_BASE where appropriate.
This CL leaves chip/npcx in a broken state -- it's fixed in a follow-up
CL.
BRANCH=None
BUG=chrome-os-partner:23796
TEST=With entire patch series, on both Samus and Glados:
- Verify 'version' EC console command is correct
- Verify 'flashrom -p ec -r read.bin' reads back EC image
- Verify software sync correctly flashes both EC and PD RW images
Change-Id: Idb3c4ed9f7f6edd0a6d49ad11753eba713e67a80
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/297484
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Diffstat (limited to 'common/rwsig.c')
| -rw-r--r-- | common/rwsig.c | 8 |
1 files changed, 5 insertions, 3 deletions
diff --git a/common/rwsig.c b/common/rwsig.c index ef86c19c23..c58e7ab84d 100644 --- a/common/rwsig.c +++ b/common/rwsig.c @@ -25,12 +25,13 @@ const struct rsa_public_key pkey __attribute__((section(".rsa_pubkey"))) = #include "gen_pub_key.h" /* The RSA signature is stored at the end of the RW firmware */ -static const void *rw_sig = (void *)CONFIG_FLASH_BASE + CONFIG_RW_MEM_OFF +static const void *rw_sig = (void *)CONFIG_PROGRAM_MEMORY_BASE + + CONFIG_RW_MEM_OFF + CONFIG_RW_SIZE - RSANUMBYTES; /* RW firmware reset vector */ static uint32_t * const rw_rst = - (uint32_t *)(CONFIG_FLASH_BASE+CONFIG_RW_MEM_OFF+4); + (uint32_t *)(CONFIG_PROGRAM_MEMORY_BASE + CONFIG_RW_MEM_OFF + 4); void check_rw_signature(void) { @@ -59,7 +60,8 @@ void check_rw_signature(void) /* SHA-256 Hash of the RW firmware */ /* TODO(crosbug.com/p/44803): Do we have to hash the whole region? */ SHA256_init(&ctx); - SHA256_update(&ctx, (void *)CONFIG_FLASH_BASE + CONFIG_RW_MEM_OFF, + SHA256_update(&ctx, (void *)CONFIG_PROGRAM_MEMORY_BASE + + CONFIG_RW_MEM_OFF, CONFIG_RW_SIZE - RSANUMBYTES); hash = SHA256_final(&ctx); |