diff options
| author | Andrey Petrov <andrey.petrov@intel.com> | 2015-06-10 10:33:39 -0700 |
|---|---|---|
| committer | ChromeOS Commit Bot <chromeos-commit-bot@chromium.org> | 2015-07-16 18:47:22 +0000 |
| commit | ef4d930f88ecf150bffa5761af72e7fa68b77afd (patch) | |
| tree | 18326cf15cbadd91030fbc5ca988bd7ee45e00ff /common/spi_flash.c | |
| parent | d705a4d208826a3666e4c201a6379434bc8695e8 (diff) | |
| download | chrome-ec-ef4d930f88ecf150bffa5761af72e7fa68b77afd.tar.gz | |
cyan: fix issues with write protection
* Fixes cyan/board.h to use correct SPI part
* Adds new flash protection regions in spi_flash_reg.c
* Sets SRP register in flash_physical_protect_at_boot()
* Fixes a bug in COMPARE_BIT macro
* Makes spi_flash_set_status() fail only when both HW pin is asserted
AND SRP(s) are set
* Makes sure set_flash_set_status() completes before returning
BUG=chrome-os-partner:40908
BRANCH=master
TEST=on Cyan:
With WP pin de-asserted:
flashrom -p ec --wp-enable
flashrom -p ec --wp-status, make sure it is enabled
flashrom -p ec --wp-disable
flashrom -p ec --status, make sure it is disabled
flashrom -p ec --wp-enable
Assert WP pin (either with screwdriver or dut-control)
flashrom -p ec --wp-disable
make sure it failed
Change-Id: I338cc906b73e723fdbb37f7c2fd0c4da358b6c8e
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/276671
Reviewed-by: Shawn N <shawnn@chromium.org>
Tested-by: Divya Jyothi <divya.jyothi@intel.com>
Commit-Queue: Divya Jyothi <divya.jyothi@intel.com>
Diffstat (limited to 'common/spi_flash.c')
| -rw-r--r-- | common/spi_flash.c | 10 |
1 files changed, 8 insertions, 2 deletions
diff --git a/common/spi_flash.c b/common/spi_flash.c index 126e38d7f7..417f97dfd1 100644 --- a/common/spi_flash.c +++ b/common/spi_flash.c @@ -15,6 +15,8 @@ #include "timer.h" #include "util.h" #include "watchdog.h" +#include "ec_commands.h" +#include "flash.h" /* * Time to sleep when chip is busy @@ -109,8 +111,9 @@ int spi_flash_set_status(int reg1, int reg2) uint8_t cmd[3] = {SPI_FLASH_WRITE_SR, reg1, reg2}; int rv = EC_SUCCESS; - /* Register has protection */ - if (spi_flash_check_wp() != SPI_WP_NONE) + /* fail if both HW pin is asserted and SRP(s) is 1 */ + if (spi_flash_check_wp() != SPI_WP_NONE && + (flash_get_protect() & EC_FLASH_PROTECT_GPIO_ASSERTED) != 0) return EC_ERROR_ACCESS_DENIED; /* Enable writing to SPI flash */ @@ -130,6 +133,9 @@ int spi_flash_set_status(int reg1, int reg2) if (rv) return rv; + /* SRP update takes up to 10 ms, so wait for transaction to finish */ + spi_flash_wait(); + return rv; } |