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| author | David Hendricks <dhendrix@chromium.org> | 2016-08-02 16:37:08 -0700 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2016-09-09 02:58:38 -0700 |
| commit | 87083d7f1862284ed4ce9d188f8e2c44392218a9 (patch) | |
| tree | c076126e9b4a116a02d0bff53c54f99aaf1d718d /common/spi_flash_reg.c | |
| parent | b9a55a09ecc891131444f1df422306357005fa0c (diff) | |
| download | chrome-ec-87083d7f1862284ed4ce9d188f8e2c44392218a9.tar.gz | |
spi_flash: Add GD25LQ40 write-protect support
This adds support for the GD25LQ40 NOR flash chip which is identical
to W25Q40 for the purposes of write-protection support for the ranges
that we care about.
BUG=chrome-os-partner:57015
BRANCH=none
TEST=needs testing
Change-Id: I09ad02e04fab4c539b9558180d73bf6c31da6aed
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/382641
Reviewed-by: Shawn N <shawnn@chromium.org>
Diffstat (limited to 'common/spi_flash_reg.c')
| -rw-r--r-- | common/spi_flash_reg.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/common/spi_flash_reg.c b/common/spi_flash_reg.c index f3c372c838..f578eff927 100644 --- a/common/spi_flash_reg.c +++ b/common/spi_flash_reg.c @@ -44,8 +44,9 @@ static const struct protect_range spi_flash_protect_ranges[] = { { X, X, 1, { 0, 1, 0 }, 0, 0x20000 }, /* Lower 1/4 */ }; -#elif defined(CONFIG_SPI_FLASH_W25Q40) +#elif defined(CONFIG_SPI_FLASH_W25Q40) || defined(CONFIG_SPI_FLASH_GD25LQ40) /* Verified for W25Q40BV and W25Q40EW */ +/* For GD25LQ40, BP3 and BP4 have same meaning as TB and SEC */ static const struct protect_range spi_flash_protect_ranges[] = { /* CMP = 0 */ { 0, X, X, { 0, 0, 0 }, 0, 0 }, /* No protection */ |