diff options
| author | Ayushee <ayushee.shah@intel.com> | 2020-04-30 14:48:37 -0700 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2020-05-05 01:14:43 +0000 |
| commit | b97108239ef5dc2eea1076c1d25878179fe5305a (patch) | |
| tree | 0b38e2342fe98b997ce1eec40c1a2441f2510047 /common/usb_pd_policy.c | |
| parent | 3d571aeec1e9b6b45576c619f359e5fe0a18f8dd (diff) | |
| download | chrome-ec-b97108239ef5dc2eea1076c1d25878179fe5305a.tar.gz | |
usb4: Override USB4 cable speed based on board design
Limit the USB4 cable speed according to the port, if the port supports
lesser USB4 speed than the cable.
Ref: TGL PDG
3.1: Fiberweave Impact for HSIOs Operating at ≥8 GT/s Speeds
MAX TBT routing length is 205mm prior to connection to re-timer
BUG=b:155429028
BRANCH=None
TEST=Tested on Volteer with 40Gbps passive cable, able to limit USB4 cable
speed to 20Gbps on Port 1 and restrict USB4 PD-flow on port 0
Change-Id: I317215d3149dae4eeca68149694ad857be5ead35
Signed-off-by: Ayushee <ayushee.shah@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2175163
Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Keith Short <keithshort@chromium.org>
Diffstat (limited to 'common/usb_pd_policy.c')
| -rw-r--r-- | common/usb_pd_policy.c | 24 |
1 files changed, 23 insertions, 1 deletions
diff --git a/common/usb_pd_policy.c b/common/usb_pd_policy.c index e169bfb994..4721fcc07d 100644 --- a/common/usb_pd_policy.c +++ b/common/usb_pd_policy.c @@ -369,6 +369,28 @@ static inline void disable_usb4_mode(int port) } /* + * For Cable rev 3.0: USB4 cable speed is set according to speed supported by + * the port and the response received from the cable, whichever is least. + * + * For Cable rev 2.0: Since board_is_tbt_usb4_port() should not enabled if the + * port supports speed less than USB_R20_SS_U31_GEN1_GEN2, USB4 cable speed is + * set according to the cable response. + */ +static void set_max_usb4_cable_speed(int port) +{ + /* + * Converting Thunderbolt-Compatible board speed to equivalent USB4 + * speed. + */ + enum usb_rev30_ss max_usb4_speed = + board_get_max_tbt_speed(port) == TBT_SS_TBT_GEN3 ? + USB_R30_SS_U40_GEN3 : USB_R30_SS_U32_U40_GEN2; + + if (max_usb4_speed < cable[port].attr.p_rev30.ss) + cable[port].attr.p_rev30.ss = max_usb4_speed; +} + +/* * Ref: USB Type-C Cable and Connector Specification * Figure 5-1 USB4 Discovery and Entry Flow Model. * @@ -406,12 +428,12 @@ static bool is_cable_ready_to_enter_usb4(int port, int cnt) { /* TODO: USB4 enter mode for Active cables */ - /* TODO: Check for port's maximum supported Thunderbolt speed */ if (IS_ENABLED(CONFIG_USB_PD_USB4) && (get_usb_pd_cable_type(port) == IDH_PTYPE_PCABLE) && is_vdo_present(cnt, VDO_INDEX_PTYPE_CABLE1)) { switch (cable[port].rev) { case PD_REV30: + set_max_usb4_cable_speed(port); switch (cable[port].attr.p_rev30.ss) { case USB_R30_SS_U40_GEN3: case USB_R30_SS_U32_U40_GEN1: |