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| author | Patryk Duda <pdk@semihalf.com> | 2020-12-29 15:03:37 +0100 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2021-02-11 08:44:28 +0000 |
| commit | 3d2d58cdb139c18cc8bcb96b8ee4be3eb2290c2d (patch) | |
| tree | 2a65d4fea04ed84730e5be6a1f5f3323949c17ba /common/usbc/usb_tc_drp_acc_trysrc_sm.c | |
| parent | 74886bcc173fa0d11e1508d412a4be390b96edad (diff) | |
| download | chrome-ec-3d2d58cdb139c18cc8bcb96b8ee4be3eb2290c2d.tar.gz | |
TCPMv2: Decrease Low Power Mode debounce delay to 10 ms
This patch decreases PD_LPM_DEBOUNCE to 10 ms. With current
100 ms delay ANX7447 can't go to Low Power Mode due to silicon
bug (b:77544959). When DRP mode is enabled ANX7447 triggers alert
every 39.7 ms. Checking what caused an alert involves I2C
transaction which changes timeout after which TCPC goes to Low
Power Mode to get_time().val + PD_LPM_DEBOUNCE_US. As a result it
is not possible to put TCPC to LPM which is necessary to work
properly (b:149761477)
Original value for PD_LPM_DEBOUNCE_US was 10 ms, introduced
in CL:1119255. This value is still used in TCPMv1.
For TCPMv2, PD_LPM_DEBOUNCE_US was changed to 100 ms in CL:2126078.
It is unclear why this value was changed. Review discussion and bug
b:149772936 don't mention why we needed to change that, so we change
it back to 10 ms for consistency with TCPMv1.
Issue was found when running EC ToT with TCPMv2 enabled on bobba board.
This CL is reland of commit 5ff18dfd6ab67df2e62c6af9f20ed472808de707
which was reverted by commit c1850a39b02cfcb7ff45282078ad606bc3526649
due to issue with TUSB422 and RT1715 chips. Issue was masked when
PD_LPM_DEBOUNCE_US was set to 100ms (actually when LPM debounce delay
was greater than tDRP). See b:176986511 for more details.
RT1715 was fixed by CL:2671265
TUSB422 was fixed by CL:2682482
BUG=b:161775827, b:77544959, b:149761477
BRANCH=none
TEST=Flash EC ToT on octopus board with ANX7447 (eg. bobba).
Make sure that DRP mode is enabled. Connect charger to port
with ANX7447 chip. Make sure that EC can connect with charger.
TEST=Flash EC ToT on Voxel board (with RT1715 TCPC) connect power sink
eg. pendrive and check if it is detected correctly.
TEST=Flash EC ToT on Volteer board (with TUSB422 TCPC) connect power
sink eg. pendrive and check if it is detected correctly.
Signed-off-by: Patryk Duda <pdk@semihalf.com>
Change-Id: If0429ea2a28f64f510ca9156f72f9cceadda9ab6
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2686411
Reviewed-by: Edward Hill <ecgh@chromium.org>
Diffstat (limited to 'common/usbc/usb_tc_drp_acc_trysrc_sm.c')
| -rw-r--r-- | common/usbc/usb_tc_drp_acc_trysrc_sm.c | 9 |
1 files changed, 7 insertions, 2 deletions
diff --git a/common/usbc/usb_tc_drp_acc_trysrc_sm.c b/common/usbc/usb_tc_drp_acc_trysrc_sm.c index 741556a594..3737d6d7a5 100644 --- a/common/usbc/usb_tc_drp_acc_trysrc_sm.c +++ b/common/usbc/usb_tc_drp_acc_trysrc_sm.c @@ -131,8 +131,13 @@ void print_flag(int port, int set_or_clear, int flag); #define CLR_FLAGS_ON_DISCONNECT(port) TC_CLR_FLAG(port, \ ~(TC_FLAGS_LPM_ENGAGED | TC_FLAGS_REQUEST_SUSPEND | TC_FLAGS_SUSPENDED)) -/* 100 ms is enough time for any TCPC transaction to complete. */ -#define PD_LPM_DEBOUNCE_US (100 * MSEC) +/* + * 10 ms is enough time for any TCPC transaction to complete + * + * This value must be below ~39.7 ms to put ANX7447 into LPM due to bug in + * silicon (see b/77544959 and b/149761477 for more details). + */ +#define PD_LPM_DEBOUNCE_US (10 * MSEC) /* * This delay is not part of the USB Type-C specification or the USB port |