diff options
| author | Aaron Durbin <adurbin@chromium.org> | 2013-05-22 12:41:08 -0500 |
|---|---|---|
| committer | ChromeBot <chrome-bot@google.com> | 2013-05-22 12:29:11 -0700 |
| commit | 3ca68b3134ae53f707a464458060d45f0a8a9ce4 (patch) | |
| tree | e7877a66ba29a6e6b79747e48d838843bd176526 /common | |
| parent | 93ec62ebc3ae238749915f8161a2673a7d2928d9 (diff) | |
| download | chrome-ec-3ca68b3134ae53f707a464458060d45f0a8a9ce4.tar.gz | |
haswell: fix RCIN# GPIO setting
The gpio pin used for RCIN# should be configured as open drain as the
rail is pulled up by a non-EC rail. Driving it high would leak power.
The current GPIO_HI_Z macro uses GPIO_HIGH as the default state.
However, it has been found that this actually drives the pin to ground.
It is still unclear how Link works or doesn't.
BUG=chrome-os-partner:19355
BRANCH=none
TEST=manual: boot on slippy without RCIN# causing reset and
the 'apreset warm' EC command works as expected.
Change-Id: I71425075f8d77b3d7e576a59fc24f823790e2655
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/56269
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Diffstat (limited to 'common')
| -rw-r--r-- | common/x86_power_haswell.c | 10 |
1 files changed, 7 insertions, 3 deletions
diff --git a/common/x86_power_haswell.c b/common/x86_power_haswell.c index ecc18624af..9185053174 100644 --- a/common/x86_power_haswell.c +++ b/common/x86_power_haswell.c @@ -237,10 +237,14 @@ void chipset_reset(int cold_reset) * PLTRST# to reset the rest of the system. */ - /* Pulse must be at least 16 PCI clocks long = 500 ns */ - gpio_set_level(GPIO_PCH_RCIN_L, 0); - udelay(10); + /* + * Pulse must be at least 16 PCI clocks long = 500 ns. The gpio + * pin used by the EC is configured as open drain. Therefore, + * the driving RCIN# low needs to the level 1 to enable the + * FET and 0 to disable the FET. */ gpio_set_level(GPIO_PCH_RCIN_L, 1); + udelay(10); + gpio_set_level(GPIO_PCH_RCIN_L, 0); } } |