diff options
| author | Nicolas Boichat <drinkcat@chromium.org> | 2018-12-28 11:26:03 +0800 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2019-01-24 00:51:29 -0800 |
| commit | d7579bd4589d08eeabf7c01f055b925acb7aed67 (patch) | |
| tree | 3adead141ceea596ac42f0ed05e2aa59d47a41d1 /common | |
| parent | 3cd175cd9ddec3fd88153b3edb9e1d7e4526420d (diff) | |
| download | chrome-ec-d7579bd4589d08eeabf7c01f055b925acb7aed67.tar.gz | |
mt_scp: Add support to store some code in DRAM
This allows to store specific code/data in a .dram region. This
is used by mt_scp to run code off DRAM, as we plan to have more
code than what can fit in SRAM.
BRANCH=none
BUG=b:122058243
TEST=make BOARD=kukui_scp -j
objdump -x build/kukui_scp/ec.obj
=> Some code is loaded in DRAM
TEST=Load kukui_scp, icachetest works
Change-Id: Idbab809ba86cabe3b984944adc2781b37d2d544b
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1391542
Diffstat (limited to 'common')
| -rw-r--r-- | common/firmware_image.S | 8 | ||||
| -rw-r--r-- | common/firmware_image.lds.S | 9 |
2 files changed, 17 insertions, 0 deletions
diff --git a/common/firmware_image.S b/common/firmware_image.S index a19968994f..a0924979c2 100644 --- a/common/firmware_image.S +++ b/common/firmware_image.S @@ -16,6 +16,8 @@ #define STRINGIFY(name) STRINGIFY0(name) #define FW_IMAGE(sect,suffix) \ STRINGIFY(FW_FILE(FINAL_OUTDIR,PROJECT,sect,suffix,)) +#define FW_IMAGE_DRAM(sect,suffix) \ + STRINGIFY(FW_FILE(FINAL_OUTDIR,PROJECT,sect,suffix,.dram)) #define FW_IMAGE_SIGN(sect,suffix) \ STRINGIFY(FW_FILE(FINAL_OUTDIR,PROJECT,sect,suffix,.sig)) @@ -56,6 +58,12 @@ .incbin FW_IMAGE_SIGN(RW,) #endif +#ifdef CONFIG_DRAM_BASE +/* Read Write firmware in DRAM */ +.section .image.RW.dram, "ax" +.incbin FW_IMAGE_DRAM(RW,) +#endif + #ifdef CONFIG_RW_B #ifdef CONFIG_RWSIG_TYPE_RWSIG .section .image.RW_B, "ax" diff --git a/common/firmware_image.lds.S b/common/firmware_image.lds.S index 8e82dcf1de..afae2f1624 100644 --- a/common/firmware_image.lds.S +++ b/common/firmware_image.lds.S @@ -40,6 +40,9 @@ OUTPUT_ARCH(BFD_ARCH) MEMORY { FLASH (rx) : ORIGIN = CONFIG_PROGRAM_MEMORY_BASE, LENGTH = CONFIG_FLASH_SIZE +#ifdef CONFIG_DRAM_BASE + DRAM (rx) : ORIGIN = CONFIG_DRAM_BASE_LOAD, LENGTH = CONFIG_DRAM_SIZE +#endif } SECTIONS { @@ -87,4 +90,10 @@ SECTIONS .padding : AT(CONFIG_PROGRAM_MEMORY_BASE + CONFIG_FLASH_SIZE - 1) { BYTE(0xff); } > FLASH =0xff + +#ifdef CONFIG_DRAM_BASE + .image.RW.dram : AT(CONFIG_DRAM_BASE_LOAD) { + *(.image.RW.dram) + } > DRAM =0x00 +#endif } |