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authorBill Richardson <wfrichar@chromium.org>2016-08-02 18:25:13 -0700
committerchrome-bot <chrome-bot@chromium.org>2016-08-05 11:45:25 -0700
commitf1bd67dedcd9c81b965ac54b8d93828b98192dc5 (patch)
treebd45058cc7bbb16b5381599b29370265ea7668f5 /common
parentcef1e7fa9a1b3a098994afcdcab0143dea890047 (diff)
downloadchrome-ec-f1bd67dedcd9c81b965ac54b8d93828b98192dc5.tar.gz
g: Decode more reasons for chip reset
There are few reasons why the SoC may reboot which we haven't been reporting (they just show up as "[Reset cause: other]"). This adds a bit of decoding to explain some of those "other" reasons. BUG=none BRANCH=none TEST=make buildall; try on Cr50 I tested one of the new reasons using "crash hang". It shows up correctly as "{Reset cause: security]". I haven't specifically tested all of the new reasons, but since this is basically just a change to console message they should work too. I'll double-check those cases once some blocking bugs are fixed. Change-Id: I46daed29d7e37bda9034a3486127bed0ea25f803 Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/366400 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Diffstat (limited to 'common')
-rw-r--r--common/system.c3
1 files changed, 2 insertions, 1 deletions
diff --git a/common/system.c b/common/system.c
index 345328749a..3b1e0ccbc7 100644
--- a/common/system.c
+++ b/common/system.c
@@ -85,7 +85,8 @@ static struct jump_data *jdata;
static const char * const reset_flag_descs[] = {
"other", "reset-pin", "brownout", "power-on", "watchdog", "soft",
"hibernate", "rtc-alarm", "wake-pin", "low-battery", "sysjump",
- "hard", "ap-off", "preserved", "usb-resume"};
+ "hard", "ap-off", "preserved", "usb-resume", "rdd", "rbox",
+ "security" };
static uint32_t reset_flags;
static int jumped_to_image;