diff options
| author | martin yan <martin.yan@microchip.corp-partner.google.com> | 2021-08-05 10:41:42 -0400 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2021-08-06 19:19:17 +0000 |
| commit | 1b3e74bc3ba38aae245f8958c012f7e4c18447d6 (patch) | |
| tree | caf22f8b10bef9f04269e45abd290bf801402b5a /common | |
| parent | b3f5db5be78e15290dc7d80eaeecbb0f1b754a2c (diff) | |
| download | chrome-ec-1b3e74bc3ba38aae245f8958c012f7e4c18447d6.tar.gz | |
mchp: Optimize spi_flash_read() API
Optimize SPI flash read timing, MEC172x QMSPI controller controls CS#
by hardware, it will add several system clock cycles delay between CS
deassertion to CS assertion at the start of the next transaction, this
guarantees SPI back to back transactions, so 1ms delay can be removed
to optimze timing.
BUG=none
BRANCH=none
TEST=Tested on ADL RVP and MCHP1727 MECC system via FAFT ECBootTime job
save 720ms as EC performs 180KB RW code's SHA256 hash computation
Signed-off-by: martin yan <martin.yan@microchip.corp-partner.google.com>
Change-Id: I5cf9c668efb1cd008b91cdd8aa09f7351c017af0
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3074767
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Diffstat (limited to 'common')
| -rw-r--r-- | common/spi_flash.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/common/spi_flash.c b/common/spi_flash.c index 1ee39e78d8..e202e1e17d 100644 --- a/common/spi_flash.c +++ b/common/spi_flash.c @@ -170,7 +170,7 @@ int spi_flash_read(uint8_t *buf_usr, unsigned int offset, unsigned int bytes) read_size); if (ret != EC_SUCCESS) break; - msleep(1); + msleep(CONFIG_SPI_FLASH_READ_WAIT_MS); } return ret; } |