diff options
author | Sam Hurst <shurst@google.com> | 2020-02-05 08:33:32 -0800 |
---|---|---|
committer | Commit Bot <commit-bot@chromium.org> | 2020-02-08 07:15:08 +0000 |
commit | a4f7c8ef7c0b9b3206f67299414c2cbd2a5fe84a (patch) | |
tree | 524e123869185318c3c1779a65079ca055c1770e /common | |
parent | dc77f10578a33ef0d3450623bf5a648d42606d8b (diff) | |
download | chrome-ec-a4f7c8ef7c0b9b3206f67299414c2cbd2a5fe84a.tar.gz |
TCPMv2: Don't exit DP mode on chipset suspend and resume
A PD_EVENT_POWER_STATE_CHANGE event was generated on a
chipset suspend/resume. If DP mode was active, the
PD_EVENT_POWER_STATE_CHANGE event would cause the
DP mode to exit. To prevent this, the event will
not be generated on chipset suspend/resume.
BUG=b:147265554
BRANCH=none
TEST=make -j buildall
manual: Connected DP to chromebook and verified
DP mode was not exited on chipset
suspend nd resume.
Change-Id: I9c6d320407376fa9b97211a7c5d0c564174bdcc3
Signed-off-by: Sam Hurst <shurst@google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2039504
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Diffstat (limited to 'common')
-rw-r--r-- | common/usbc/usb_tc_drp_acc_trysrc_sm.c | 11 |
1 files changed, 8 insertions, 3 deletions
diff --git a/common/usbc/usb_tc_drp_acc_trysrc_sm.c b/common/usbc/usb_tc_drp_acc_trysrc_sm.c index 352552f576..51e2938772 100644 --- a/common/usbc/usb_tc_drp_acc_trysrc_sm.c +++ b/common/usbc/usb_tc_drp_acc_trysrc_sm.c @@ -1301,15 +1301,20 @@ static void handle_new_power_state(int port) { if (IS_ENABLED(CONFIG_POWER_COMMON) && IS_ENABLED(CONFIG_USB_PE_SM)) { - if (chipset_in_or_transitioning_to_state(CHIPSET_STATE_ANY_OFF)) + if (chipset_in_or_transitioning_to_state( + CHIPSET_STATE_ANY_OFF)) { /* * The SoC will negotiated DP mode again when it * boots up */ pe_exit_dp_mode(port); - /* Ensure mux is set properly after chipset transition */ - set_usb_mux_with_current_data_role(port); + /* + * Reset mux to USB. DP mode is selected + * again at boot up. + */ + set_usb_mux_with_current_data_role(port); + } } } #endif /* CONFIG_POWER_COMMON */ |