diff options
| author | Namyoon Woo <namyoon@google.com> | 2020-05-13 19:09:35 -0700 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2020-06-01 17:49:45 +0000 |
| commit | 77f11cd9e99bc1d6a63acee45a3d457b7f205523 (patch) | |
| tree | 801ab6fb0ad27213797a09026645d62d8c3708d4 /common | |
| parent | 5a60b3b215125e8d2c145e17867fcfaaae682dcd (diff) | |
| download | chrome-ec-77f11cd9e99bc1d6a63acee45a3d457b7f205523.tar.gz | |
Introduce TPM_BOARD_CFG register
This patch adds the TPM vendor-defined register, TPM_BOARD_CFG,
which indicates the board configuration status. This register is
attributed as one-time-programmable and the value is maintained
across deep sleeps. Cr50 allows a write on this register right after
a cr50 reset until it receives a TPM2_PCR_Extend command.
BUG=b:148691139
TEST=none
Signed-off-by: Namyoon Woo <namyoon@google.com>
Change-Id: I89ae5a53c15990ef78812aec5da81a59f04d7d98
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2202838
Tested-by: Namyoon Woo <namyoon@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Commit-Queue: Namyoon Woo <namyoon@chromium.org>
Diffstat (limited to 'common')
| -rw-r--r-- | common/i2cs_tpm.c | 1 | ||||
| -rw-r--r-- | common/tpm_registers.c | 25 |
2 files changed, 26 insertions, 0 deletions
diff --git a/common/i2cs_tpm.c b/common/i2cs_tpm.c index d76befcbee..edbe7aa967 100644 --- a/common/i2cs_tpm.c +++ b/common/i2cs_tpm.c @@ -77,6 +77,7 @@ static const struct i2c_tpm_reg_map i2c_to_tpm[] = { {0xa, 4, 0x14}, /* TPM TPM_INTF_CAPABILITY */ {0xe, 1, 0xf04}, /* TPM RID */ {0xf, 0, 0xf90}, /* TPM_FW_VER */ + {0x1c, 4, 0xfe0}, /* TPM_BOARD_CFG */ }; /* Used to track number of times i2cs hw read fifo was adjusted */ diff --git a/common/tpm_registers.c b/common/tpm_registers.c index d2862d5814..db2cba9b88 100644 --- a/common/tpm_registers.c +++ b/common/tpm_registers.c @@ -85,6 +85,7 @@ #define TPM_DID_VID (0xf00) #define TPM_RID (0xf04) #define TPM_FW_VER (0xf90) +#define TPM_BOARD_CFG (0xfe0) #define GOOGLE_VID 0x1ae0 #define GOOGLE_DID 0x0028 @@ -417,6 +418,17 @@ static void fifo_reg_write(const uint8_t *data, uint32_t data_size) tpm_.regs.sts &= ~expect; } +/* Collect received data and write that value on TPM_BOARD_CFG register. */ +static void board_cfg_reg_write_(const uint8_t *data, uint32_t data_size) +{ + uint32_t value = 0; + + data_size = MIN(data_size, sizeof(value)); + memcpy(&value, data, data_size); + + board_cfg_reg_write(value); +} + /* TODO: data_size is between 1 and 64, but is not trustworthy! Don't write * past the end of any actual registers if data_size is larger than the spec * allows. */ @@ -446,6 +458,9 @@ void tpm_register_put(uint32_t regaddr, const uint8_t *data, uint32_t data_size) /* Reset read byte count */ tpm_fw_ver_index = 0; break; + case TPM_BOARD_CFG: + board_cfg_reg_write_(data, data_size); + break; default: CPRINTF("%s(0x%06x, %d bytes:", __func__, regaddr, data_size); for (i = 0; i < data_size; i++) @@ -539,6 +554,9 @@ void tpm_register_get(uint32_t regaddr, uint8_t *dest, uint32_t data_size) *dest++ = 0; } break; + case TPM_BOARD_CFG: + copy_bytes(dest, data_size, board_cfg_reg_read()); + break; default: CPRINTS("%s(0x%06x, %d) => ??", __func__, regaddr, data_size); return; @@ -1033,6 +1051,13 @@ void tpm_task(void *u) */ if (command_code == TPM2_PCR_Read) system_process_retry_counter(); + else if (command_code == TPM2_PCR_Extend) + /* + * Cr50 recognizes BIOS-RO exit indirectly + * by this command. + */ + board_cfg_reg_write_disable(); + #ifdef CONFIG_EXTENSION_COMMAND if (!IS_CUSTOM_CODE(command_code)) #endif |