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| author | Vincent Palatin <vpalatin@chromium.org> | 2018-03-01 16:45:40 +0100 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2018-03-02 06:49:06 -0800 |
| commit | f23f45e74e4c0aff7116a832556d194747997ffe (patch) | |
| tree | 348f7a5a727346f0317155b84938488c68e78a48 /core/cortex-m/cpu.h | |
| parent | c55f09496009249426574e1facf96a222b4e4693 (diff) | |
| download | chrome-ec-f23f45e74e4c0aff7116a832556d194747997ffe.tar.gz | |
cortex-m: enable I-cache on ARMv7-M
The ARMv7-M ISA defines standard (and optional) mechanism to manage the
CPU caches through the SCB (System Control Block) registers.
So far, only the Cortex-M7 core implements such as a mechanism (e.g. the
Cortex-M4 with caches we have are using a proprietary mechanism for the
management).
Define the functions to use the I-Cache,
and enable them on STM32H7 which is our only supported Cortex-M7 core.
The D-Cache mechanism is still To Be Done, as it involves a bit more
support in the firmware for the DMA memory areas.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=b:67081508
TEST=on ZerbleBarn, verify manually that the 'IC' bit is set in the CCR
(e.g. 'rw 0xe000ed14' returns 0x60218), and runs some CPU workload
without crash and with a speed-up.
Change-Id: I6af1021d65048b787630387f7d95797db15d069c
Reviewed-on: https://chromium-review.googlesource.com/943445
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Diffstat (limited to 'core/cortex-m/cpu.h')
| -rw-r--r-- | core/cortex-m/cpu.h | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/core/cortex-m/cpu.h b/core/cortex-m/cpu.h index 07e1c4b543..f4400a0444 100644 --- a/core/cortex-m/cpu.h +++ b/core/cortex-m/cpu.h @@ -41,6 +41,8 @@ enum { CPU_NVIC_MMFS_BFARVALID = 1 << 15, CPU_NVIC_MMFS_MFARVALID = 1 << 7, + CPU_NVIC_CCR_ICACHE = 1 << 17, + CPU_NVIC_CCR_DCACHE = 1 << 16, CPU_NVIC_CCR_DIV_0_TRAP = 1 << 4, CPU_NVIC_CCR_UNALIGN_TRAP = 1 << 3, @@ -53,7 +55,15 @@ enum { CPU_NVIC_SHCSR_USGFAULTENA = 1 << 18, }; +/* System Control Block: cache registers */ +#define CPU_SCB_CCSIDR CPUREG(0xe000ed80) +#define CPU_SCB_CCSELR CPUREG(0xe000ed84) +#define CPU_SCB_ICIALLU CPUREG(0xe000ef50) +#define CPU_SCB_DCISW CPUREG(0xe000ef60) + /* Set up the cpu to detect faults */ void cpu_init(void); +/* Enable the CPU instruction cache if it is not already enabled */ +void cpu_enable_icache(void); #endif /* __CROS_EC_CPU_H */ |