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| author | Gwendal Grignou <gwendal@chromium.org> | 2019-03-11 15:57:52 -0700 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2019-03-26 04:42:55 -0700 |
| commit | bb266fc26fc05d4ab22de6ad7bce5b477c9f9140 (patch) | |
| tree | f6ada087f62246c3a9547e649ac8846b0ed6d5ab /core/cortex-m/cpu.h | |
| parent | 0bfc511527cf2aebfa163c63a1d028419ca0b0c3 (diff) | |
| download | chrome-ec-bb266fc26fc05d4ab22de6ad7bce5b477c9f9140.tar.gz | |
common: replace 1 << digits, with BIT(digits)
Requested for linux integration, use BIT instead of 1 <<
First step replace bit operation with operand containing only digits.
Fix an error in motion_lid try to set bit 31 of a signed integer.
BUG=None
BRANCH=None
TEST=compile
Change-Id: Ie843611f2f68e241f0f40d4067f7ade726951d29
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1518659
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Diffstat (limited to 'core/cortex-m/cpu.h')
| -rw-r--r-- | core/cortex-m/cpu.h | 31 |
1 files changed, 16 insertions, 15 deletions
diff --git a/core/cortex-m/cpu.h b/core/cortex-m/cpu.h index 87e0631787..21de5bebf4 100644 --- a/core/cortex-m/cpu.h +++ b/core/cortex-m/cpu.h @@ -9,15 +9,16 @@ #define __CROS_EC_CPU_H #include <stdint.h> +#include "compile_time_macros.h" /* Macro to access 32-bit registers */ #define CPUREG(addr) (*(volatile uint32_t*)(addr)) #define CPU_NVIC_ST_CTRL CPUREG(0xE000E010) -#define ST_ENABLE (1 << 0) -#define ST_TICKINT (1 << 1) -#define ST_CLKSOURCE (1 << 2) -#define ST_COUNTFLAG (1 << 16) +#define ST_ENABLE BIT(0) +#define ST_TICKINT BIT(1) +#define ST_CLKSOURCE BIT(2) +#define ST_COUNTFLAG BIT(16) /* Nested Vectored Interrupt Controller */ #define CPU_NVIC_EN(x) CPUREG(0xe000e100 + 4 * (x)) @@ -38,21 +39,21 @@ #define CPU_NVIC_BFAR CPUREG(0xe000ed38) enum { - CPU_NVIC_MMFS_BFARVALID = 1 << 15, - CPU_NVIC_MMFS_MFARVALID = 1 << 7, + CPU_NVIC_MMFS_BFARVALID = BIT(15), + CPU_NVIC_MMFS_MFARVALID = BIT(7), - CPU_NVIC_CCR_ICACHE = 1 << 17, - CPU_NVIC_CCR_DCACHE = 1 << 16, - CPU_NVIC_CCR_DIV_0_TRAP = 1 << 4, - CPU_NVIC_CCR_UNALIGN_TRAP = 1 << 3, + CPU_NVIC_CCR_ICACHE = BIT(17), + CPU_NVIC_CCR_DCACHE = BIT(16), + CPU_NVIC_CCR_DIV_0_TRAP = BIT(4), + CPU_NVIC_CCR_UNALIGN_TRAP = BIT(3), CPU_NVIC_HFSR_DEBUGEVT = 1UL << 31, - CPU_NVIC_HFSR_FORCED = 1 << 30, - CPU_NVIC_HFSR_VECTTBL = 1 << 1, + CPU_NVIC_HFSR_FORCED = BIT(30), + CPU_NVIC_HFSR_VECTTBL = BIT(1), - CPU_NVIC_SHCSR_MEMFAULTENA = 1 << 16, - CPU_NVIC_SHCSR_BUSFAULTENA = 1 << 17, - CPU_NVIC_SHCSR_USGFAULTENA = 1 << 18, + CPU_NVIC_SHCSR_MEMFAULTENA = BIT(16), + CPU_NVIC_SHCSR_BUSFAULTENA = BIT(17), + CPU_NVIC_SHCSR_USGFAULTENA = BIT(18), }; /* System Control Block: cache registers */ |