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| author | Vincent Palatin <vpalatin@chromium.org> | 2012-01-25 21:47:20 +0000 |
|---|---|---|
| committer | Vincent Palatin <vpalatin@chromium.org> | 2012-01-25 22:50:07 +0000 |
| commit | cf9fcef328900ae4460755cca01ec46e98b01732 (patch) | |
| tree | 19e56762b6daa2b3abb2a2d2235d72dd417b3ed3 /core/cortex-m/ec.lds.S | |
| parent | 645dad5d3f658d7c5e0d54453964e91afe7b43c0 (diff) | |
| download | chrome-ec-cf9fcef328900ae4460755cca01ec46e98b01732.tar.gz | |
Move OS files to a CPU specific directory
Preparatory work to introduce a second SoC : 3/5
We split the drivers files which contain SoC specific drivers from the
OS files which only depend the actual CPU core.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=None
TEST=run EC firmware on BDS and test a few commands on the console.
Change-Id: I598f8b23e074da9bd6b0e2ce6689c1075fe854f0
Diffstat (limited to 'core/cortex-m/ec.lds.S')
| -rw-r--r-- | core/cortex-m/ec.lds.S | 63 |
1 files changed, 63 insertions, 0 deletions
diff --git a/core/cortex-m/ec.lds.S b/core/cortex-m/ec.lds.S new file mode 100644 index 0000000000..35006ae77f --- /dev/null +++ b/core/cortex-m/ec.lds.S @@ -0,0 +1,63 @@ +/* Copyright (c) 2012 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ +#include "config.h" + +#define CONFIG_FW_SECT_OFF(section) CONFIG_FW_##section##_OFF +#define CONFIG_FW_BASE(section) (CONFIG_FLASH_BASE + CONFIG_FW_SECT_OFF(section)) + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(reset) +MEMORY +{ + FLASH (rx) : ORIGIN = CONFIG_FW_BASE(SECTION), LENGTH = CONFIG_FW_IMAGE_SIZE + IRAM (rw) : ORIGIN = CONFIG_RAM_BASE, LENGTH = CONFIG_RAM_SIZE +} +SECTIONS +{ + .text : { + OUTDIR/core/CORE/init.o (.text) + *(.text*) +#ifdef COMPILE_FOR_RAM + } > IRAM +#else + } > FLASH +#endif + . = ALIGN(4); + .rodata : { + __irqprio = .; + *(.rodata.irqprio) + __irqprio_end = .; + . = ALIGN(4); + __cmds = .; + *(.rodata.cmds) + __cmds_end = .; + *(.rodata*) + . = ALIGN(4); +#ifdef COMPILE_FOR_RAM + } > IRAM + __ro_end = . ; + .data : { +#else + } > FLASH + __ro_end = . ; + .data : AT(ADDR(.rodata) + SIZEOF(.rodata)) { +#endif + . = ALIGN(4); + __data_start = .; + *(.data.tasks) + *(.data) + . = ALIGN(4); + __data_end = .; + } > IRAM + .bss : { + . = ALIGN(4); + __bss_start = .; + *(.bss) + . = ALIGN(4); + __bss_end = .; + } > IRAM + /DISCARD/ : { *(.ARM.*) } +} |