Merge remote-tracking branch cros/main into firmware-fpmcu-bloonchipper-releasefirmware-fpmcu-bloonchipper-release

Generated by: ./util/update_release_branch.py --board bloonchipper
--relevant_paths_file ./util/fingerprint-relevant-paths.txt firmware-
fpmcu-bloonchipper-release

Relevant changes:

git log --oneline e5fb0b9ba4..28712dae9d -- board/hatch_fp
board/bloonchipper common/fpsensor docs/fingerprint driver/fingerprint
util/getversion.sh

ded9307b79 util/getversion.sh: Fix version when not in a git repo
956055e692 board: change Google USB vendor info
71b2ef709d Update license boilerplate text in source code files
33e11afda0 Revert "fpsensor: Build fpsensor source file with C++"
c8d0360723 fpsensor: Build fpsensor source file with C++
bc113abd53 fpsensor: Fix g++ compiler error
150a58a0dc fpsensor: Fix fp_set_sensor_mode return type
b33b5ce85b fpsensor: Remove nested designators for C++ compatibility
2e864b2539 tree-wide: const-ify argv for console commands
56d8b360f9 test: Add test for get ikm failure when seed not set
3a3d6c3690 test: Add test for fpsensor trivial key failure
233e6bbd08 fpsensor_crypto: Abstract calls to hmac_SHA256
0a041b285b docs/fingerprint: Typo correction
c03fab67e2 docs/fingerprint: Fix the path of fputils.py
0b5d4baf5a util/getversion.sh: Fix empty file list handling
6e128fe760 FPMCU dev board environment with Satlab
3eb29b6aa5 builtin: Move ssize_t to sys/types.h
345d62ebd1 docs/fingerprint: Update power numbers for latest dartmonkey release
c25ffdb316 common: Conditionally support printf %l and %i modifiers
9a3c514b45 test: Add a test to check if the debugger is connected
54e603413f Move standard library tests to their own file
43fa6b4bf8 docs/fingerprint: Update power numbers for latest bloonchipper release
25536f9a84 driver/fingerprint/fpc/bep/fpc_sensor_spi.c: Format with clang-format
4face99efd driver/fingerprint/fpc/libfp/fpc_sensor_pal.h: Format with clang-format
738de2b575 trng: Rename rand to trng_rand
14b8270edd docs/fingerprint: Update dragonclaw power numbers
0b268f93d1 driver/fingerprint/fpc/libfp/fpc_private.c: Format with clang-format
f80da163f2 driver/fingerprint/fpc/libfp/fpc_private.h: Format with clang-format
5e9c85c9b1 driver/fingerprint/fpc/libfp/fpc_sensor_pal.c: Format with clang-format
c1f9dd3cf8 driver/fingerprint/fpc/libfp/fpc_bio_algorithm.h: Format with clang-format
eb1e1bed8d driver/fingerprint/fpc/libfp/fpc1145_private.h: Format with clang-format
6e7b611821 driver/fingerprint/fpc/bep/fpc_bio_algorithm.h: Format with clang-format
e0589cd5e2 driver/fingerprint/fpc/bep/fpc1035_private.h: Format with clang-format
7905e556a0 common/fpsensor/fpsensor_crypto.c: Format with clang-format
21289d170c driver/fingerprint/fpc/bep/fpc1025_private.h: Format with clang-format
98a20f937e common/fpsensor/fpsensor_state.c: Format with clang-format
a2d255d8af common/fpsensor/fpsensor.c: Format with clang-format
73055eeb3f driver/fingerprint/fpc/bep/fpc_private.c: Format with clang-format
0f7b5cb509 common/fpsensor/fpsensor_private.h: Format with clang-format
1ceade6e65 driver/fingerprint/fpc/bep/fpc_private.h: Format with clang-format
dc3e9008b8 board/hatch_fp/board.h: Format with clang-format
dca9d74321 Revert "trng: Rename rand to trng_rand"
a6b0b3554f trng: Rename rand to trng_rand
28d0b75b70 third_party/boringssl: Remove unused header

BRANCH=None
BUG=b:246424843 b:234181908 b:244781166 b:234181908 b:244387210
BUG=b:242720240 chromium:1098010 b:180945056 b:236025198 b:234181908
BUG=b:234181908 b:237344361 b:131913998 b:236386294 b:234143158
BUG=b:234781655 b:215613183 b:242720910
TEST=`make -j buildall`
TEST=./test/run_device_tests.py --board bloonchipper
     Test "aes": PASSED
     Test "cec": PASSED
     Test "cortexm_fpu": PASSED
     Test "crc": PASSED
     Test "flash_physical": PASSED
     Test "flash_write_protect": PASSED
     Test "fpsensor_hw": PASSED
     Test "fpsensor_spi_ro": PASSED
     Test "fpsensor_spi_rw": PASSED
     Test "fpsensor_uart_ro": PASSED
     Test "fpsensor_uart_rw": PASSED
     Test "mpu_ro": PASSED
     Test "mpu_rw": PASSED
     Test "mutex": PASSED
     Test "pingpong": PASSED
     Test "printf": PASSED
     Test "queue": PASSED
     Test "rollback_region0": PASSED
     Test "rollback_region1": PASSED
     Test "rollback_entropy": PASSED
     Test "rtc": PASSED
     Test "sha256": PASSED
     Test "sha256_unrolled": PASSED
     Test "static_if": PASSED
     Test "stdlib": PASSED
     Test "system_is_locked_wp_on": PASSED
     Test "system_is_locked_wp_off": PASSED
     Test "timer_dos": PASSED
     Test "utils": PASSED
     Test "utils_str": PASSED
     Test "stm32f_rtc": PASSED
     Test "panic_data_bloonchipper_v2.0.4277": PASSED
     Test "panic_data_bloonchipper_v2.0.5938": PASSED

Force-Relevant-Builds: all
Signed-off-by: Tom Hughes <tomhughes@chromium.org>
Change-Id: I264ad0ffe7afcd507a1e483c6e934a9c4fea47c3

1 files changed, 33 insertions, 33 deletions

diff --git a/core/cortex-m/include/mpu.h b/core/cortex-m/include/mpu.h
index 610728b501..75f95e7000 100644
--- a/core/cortex-m/include/mpu.h
+++ b/core/cortex-m/include/mpu.h
@@ -1,4 +1,4 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -14,7 +14,7 @@
 /*
  * ARMv7-M SRAM region
  */
-#define CORTEX_M_SRAM_BASE	0x20000000
+#define CORTEX_M_SRAM_BASE 0x20000000
 
 /*
  * Region assignment. 7 as the highest, a higher index has a higher priority.
@@ -26,64 +26,64 @@
  * made mutually exclusive.
  */
 enum mpu_region {
-	REGION_DATA_RAM = 0,		/* For internal data RAM */
-	REGION_DATA_RAM2 = 1,		/* Second region for unaligned size */
-	REGION_CODE_RAM = 2,		/* For internal code RAM */
-	REGION_CODE_RAM2 = 3,		/* Second region for unaligned size */
-	REGION_STORAGE = 4,		/* For mapped internal storage */
-	REGION_STORAGE2 = 5,		/* Second region for unaligned size */
-	REGION_DATA_RAM_TEXT = 6,	/* Exempt region of data RAM */
-	REGION_CHIP_RESERVED = 7,	/* Reserved for use in chip/ */
+	REGION_DATA_RAM = 0, /* For internal data RAM */
+	REGION_DATA_RAM2 = 1, /* Second region for unaligned size */
+	REGION_CODE_RAM = 2, /* For internal code RAM */
+	REGION_CODE_RAM2 = 3, /* Second region for unaligned size */
+	REGION_STORAGE = 4, /* For mapped internal storage */
+	REGION_STORAGE2 = 5, /* Second region for unaligned size */
+	REGION_DATA_RAM_TEXT = 6, /* Exempt region of data RAM */
+	REGION_CHIP_RESERVED = 7, /* Reserved for use in chip/ */
 	/* only for chips with MPU supporting 16 regions */
-	REGION_UNCACHED_RAM = 8,        /* For uncached data RAM */
-	REGION_UNCACHED_RAM2 = 9,       /* Second region for unaligned size */
-	REGION_ROLLBACK = 10,           /* For rollback */
+	REGION_UNCACHED_RAM = 8, /* For uncached data RAM */
+	REGION_UNCACHED_RAM2 = 9, /* Second region for unaligned size */
+	REGION_ROLLBACK = 10, /* For rollback */
 };
 
-#define MPU_TYPE		REG32(0xe000ed90)
-#define MPU_CTRL		REG32(0xe000ed94)
-#define MPU_NUMBER		REG32(0xe000ed98)
-#define MPU_BASE		REG32(0xe000ed9c)
-#define MPU_SIZE		REG16(0xe000eda0)
-#define MPU_ATTR		REG16(0xe000eda2)
+#define MPU_TYPE REG32(0xe000ed90)
+#define MPU_CTRL REG32(0xe000ed94)
+#define MPU_NUMBER REG32(0xe000ed98)
+#define MPU_BASE REG32(0xe000ed9c)
+#define MPU_SIZE REG16(0xe000eda0)
+#define MPU_ATTR REG16(0xe000eda2)
 
 /*
  * See ARM v7-M Architecture Reference Manual
  * Section B3.5.5 MPU Type Register, MPU_TYPE
  */
-#define MPU_TYPE_UNIFIED_MASK	0x00FF0001
-#define MPU_TYPE_REG_COUNT(t)	(((t) >> 8) & 0xFF)
+#define MPU_TYPE_UNIFIED_MASK 0x00FF0001
+#define MPU_TYPE_REG_COUNT(t) (((t) >> 8) & 0xFF)
 
-#define MPU_CTRL_PRIVDEFEN	BIT(2)
-#define MPU_CTRL_HFNMIENA	BIT(1)
-#define MPU_CTRL_ENABLE		BIT(0)
+#define MPU_CTRL_PRIVDEFEN BIT(2)
+#define MPU_CTRL_HFNMIENA BIT(1)
+#define MPU_CTRL_ENABLE BIT(0)
 
 /*
  * Minimum region size is 32 bytes, 5 bits of address space
  */
-#define MPU_SIZE_BITS_MIN	5
+#define MPU_SIZE_BITS_MIN 5
 
 /*
  * XN (execute never) bit. It's bit 12 if accessed by halfword.
  *   0: XN off
  *   1: XN on
  */
-#define MPU_ATTR_XN		BIT(12)
+#define MPU_ATTR_XN BIT(12)
 
 /* AP bit. See table 3-5 of Stellaris LM4F232H5QC datasheet for details */
-#define MPU_ATTR_NO_NO (0 << 8)  /* previleged no access, unprev no access */
-#define MPU_ATTR_RW_NO (1 << 8)  /* previleged ReadWrite, unprev no access */
-#define MPU_ATTR_RW_RO (2 << 8)  /* previleged ReadWrite, unprev Read-only */
-#define MPU_ATTR_RW_RW (3 << 8)  /* previleged ReadWrite, unprev ReadWrite */
-#define MPU_ATTR_RO_NO (5 << 8)  /* previleged Read-only, unprev no access */
+#define MPU_ATTR_NO_NO (0 << 8) /* previleged no access, unprev no access */
+#define MPU_ATTR_RW_NO (1 << 8) /* previleged ReadWrite, unprev no access */
+#define MPU_ATTR_RW_RO (2 << 8) /* previleged ReadWrite, unprev Read-only */
+#define MPU_ATTR_RW_RW (3 << 8) /* previleged ReadWrite, unprev ReadWrite */
+#define MPU_ATTR_RO_NO (5 << 8) /* previleged Read-only, unprev no access */
 
 /* Suggested value for TEX S/C/B bit. See table 3-6 of Stellaris LM4F232H5QC
  * datasheet and table 38 of STM32F10xxx Cortex-M3 programming manual. */
 #ifndef MPU_ATTR_INTERNAL_SRAM
-#define MPU_ATTR_INTERNAL_SRAM  6  /* for Internal SRAM */
+#define MPU_ATTR_INTERNAL_SRAM 6 /* for Internal SRAM */
 #endif
 #ifndef MPU_ATTR_FLASH_MEMORY
-#define MPU_ATTR_FLASH_MEMORY   2  /* for flash memory */
+#define MPU_ATTR_FLASH_MEMORY 2 /* for flash memory */
 #endif
 
 /* Represent RW with at most 2 MPU regions. */