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| author | Shawn Nematbakhsh <shawnn@chromium.org> | 2017-11-07 16:11:03 -0800 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2017-11-14 10:11:18 -0800 |
| commit | b6991dd96d8bf6cb86a39b3da590ccd8b4e1e036 (patch) | |
| tree | b4a83fa1cb9f38bd08c76aa5f56b3e2c12c721a5 /core/cortex-m/include | |
| parent | 2a62a3dfca91a3d8f755c1cf31fb3289f1511af3 (diff) | |
| download | chrome-ec-b6991dd96d8bf6cb86a39b3da590ccd8b4e1e036.tar.gz | |
cortex-m: mpu: Support unaligned regions and protect code RAM
Support protection of regions that aren't aligned to a power of 2 by
using two MPU entries, and taking advantage of the sub-region feature.
Also protect code RAM from being overwritten, on parts that use external
storage.
BUG=chromium:782244
BRANCH=None
TEST=On kevin, call:
mpu_protect_data_ram();
mpu_protect_code_ram();
mpu_enable();
Verify that first call results in the following update_region params:
addr: 0x200c2000 size: 0xc01d
Decoded: Protect 24K region
Verify that second call results in the following params:
addr: 0x100a8000 size: 0xc021
Decoded: Protect 96K region
addr: 0x100c0000 size: 0xf01b
Decoded: Protect remaining 8K region
Also verify that writes to beginning and end of code ram region trigger
data access violation after enabling protection.
Also verify that sysjump fails.
Change-Id: Ieb7a4ec3a089e8a2d29f231e1e3acf2e78e560a1
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/757721
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Diffstat (limited to 'core/cortex-m/include')
| -rw-r--r-- | core/cortex-m/include/mpu.h | 29 |
1 files changed, 27 insertions, 2 deletions
diff --git a/core/cortex-m/include/mpu.h b/core/cortex-m/include/mpu.h index c0c595a367..bb5eaa4c7e 100644 --- a/core/cortex-m/include/mpu.h +++ b/core/cortex-m/include/mpu.h @@ -10,6 +10,26 @@ #include "common.h" +/* + * Region assignment. 7 as the highest, a higher index has a higher priority. + * For example, using 7 for .iram.text allows us to mark entire RAM XN except + * .iram.text, which is used for hibernation. + * Region assignment is currently wasteful and can be changed if more + * regions are needed in the future. For example, a second region may not + * be necessary for all types, and REGION_CODE_RAM / REGION_STORAGE can be + * made mutually exclusive. + */ +enum mpu_region { + REGION_DATA_RAM = 0, /* For internal data RAM */ + REGION_DATA_RAM2 = 1, /* Second region for unaligned size */ + REGION_CODE_RAM = 2, /* For internal code RAM */ + REGION_CODE_RAM2 = 3, /* Second region for unaligned size */ + REGION_STORAGE = 4, /* For mapped internal storage */ + REGION_STORAGE2 = 5, /* Second region for unaligned size */ + REGION_DATA_RAM_TEXT = 6, /* Exempt region of data RAM */ + REGION_CHIP_RESERVED = 7, /* Reserved for use in chip/ */ +}; + #define MPU_TYPE REG32(0xe000ed90) #define MPU_CTRL REG32(0xe000ed94) #define MPU_NUMBER REG32(0xe000ed98) @@ -60,10 +80,15 @@ extern char __iram_text_end; /** * Protect RAM from code execution */ -int mpu_protect_ram(void); +int mpu_protect_data_ram(void); + +/** + * Protect code RAM from being overwritten + */ +int mpu_protect_code_ram(void); /** - * Protect flash memory from code execution + * Protect internal mapped flash memory from code execution */ int mpu_lock_ro_flash(void); int mpu_lock_rw_flash(void); |