summaryrefslogtreecommitdiff
path: root/core/cortex-m/mpu.c
diff options
context:
space:
mode:
authorTom Hughes <tomhughes@chromium.org>2022-09-21 14:10:01 -0700
committerTom Hughes <tomhughes@chromium.org>2022-09-22 12:49:33 -0700
commit2bcf863b492fe7ed8105c853814dba6ed32ba719 (patch)
treefcf6ce5810f9ff9e3c8cce434812dd75492269ed /core/cortex-m/mpu.c
parente5fb0b9ba488614b5684e640530f00821ab7b943 (diff)
parent28712dae9d7ed1e694f7622cc083afa71090d4d5 (diff)
downloadchrome-ec-2bcf863b492fe7ed8105c853814dba6ed32ba719.tar.gz
Merge remote-tracking branch cros/main into firmware-fpmcu-bloonchipper-releasefirmware-fpmcu-bloonchipper-release
Generated by: ./util/update_release_branch.py --board bloonchipper --relevant_paths_file ./util/fingerprint-relevant-paths.txt firmware- fpmcu-bloonchipper-release Relevant changes: git log --oneline e5fb0b9ba4..28712dae9d -- board/hatch_fp board/bloonchipper common/fpsensor docs/fingerprint driver/fingerprint util/getversion.sh ded9307b79 util/getversion.sh: Fix version when not in a git repo 956055e692 board: change Google USB vendor info 71b2ef709d Update license boilerplate text in source code files 33e11afda0 Revert "fpsensor: Build fpsensor source file with C++" c8d0360723 fpsensor: Build fpsensor source file with C++ bc113abd53 fpsensor: Fix g++ compiler error 150a58a0dc fpsensor: Fix fp_set_sensor_mode return type b33b5ce85b fpsensor: Remove nested designators for C++ compatibility 2e864b2539 tree-wide: const-ify argv for console commands 56d8b360f9 test: Add test for get ikm failure when seed not set 3a3d6c3690 test: Add test for fpsensor trivial key failure 233e6bbd08 fpsensor_crypto: Abstract calls to hmac_SHA256 0a041b285b docs/fingerprint: Typo correction c03fab67e2 docs/fingerprint: Fix the path of fputils.py 0b5d4baf5a util/getversion.sh: Fix empty file list handling 6e128fe760 FPMCU dev board environment with Satlab 3eb29b6aa5 builtin: Move ssize_t to sys/types.h 345d62ebd1 docs/fingerprint: Update power numbers for latest dartmonkey release c25ffdb316 common: Conditionally support printf %l and %i modifiers 9a3c514b45 test: Add a test to check if the debugger is connected 54e603413f Move standard library tests to their own file 43fa6b4bf8 docs/fingerprint: Update power numbers for latest bloonchipper release 25536f9a84 driver/fingerprint/fpc/bep/fpc_sensor_spi.c: Format with clang-format 4face99efd driver/fingerprint/fpc/libfp/fpc_sensor_pal.h: Format with clang-format 738de2b575 trng: Rename rand to trng_rand 14b8270edd docs/fingerprint: Update dragonclaw power numbers 0b268f93d1 driver/fingerprint/fpc/libfp/fpc_private.c: Format with clang-format f80da163f2 driver/fingerprint/fpc/libfp/fpc_private.h: Format with clang-format 5e9c85c9b1 driver/fingerprint/fpc/libfp/fpc_sensor_pal.c: Format with clang-format c1f9dd3cf8 driver/fingerprint/fpc/libfp/fpc_bio_algorithm.h: Format with clang-format eb1e1bed8d driver/fingerprint/fpc/libfp/fpc1145_private.h: Format with clang-format 6e7b611821 driver/fingerprint/fpc/bep/fpc_bio_algorithm.h: Format with clang-format e0589cd5e2 driver/fingerprint/fpc/bep/fpc1035_private.h: Format with clang-format 7905e556a0 common/fpsensor/fpsensor_crypto.c: Format with clang-format 21289d170c driver/fingerprint/fpc/bep/fpc1025_private.h: Format with clang-format 98a20f937e common/fpsensor/fpsensor_state.c: Format with clang-format a2d255d8af common/fpsensor/fpsensor.c: Format with clang-format 73055eeb3f driver/fingerprint/fpc/bep/fpc_private.c: Format with clang-format 0f7b5cb509 common/fpsensor/fpsensor_private.h: Format with clang-format 1ceade6e65 driver/fingerprint/fpc/bep/fpc_private.h: Format with clang-format dc3e9008b8 board/hatch_fp/board.h: Format with clang-format dca9d74321 Revert "trng: Rename rand to trng_rand" a6b0b3554f trng: Rename rand to trng_rand 28d0b75b70 third_party/boringssl: Remove unused header BRANCH=None BUG=b:246424843 b:234181908 b:244781166 b:234181908 b:244387210 BUG=b:242720240 chromium:1098010 b:180945056 b:236025198 b:234181908 BUG=b:234181908 b:237344361 b:131913998 b:236386294 b:234143158 BUG=b:234781655 b:215613183 b:242720910 TEST=`make -j buildall` TEST=./test/run_device_tests.py --board bloonchipper Test "aes": PASSED Test "cec": PASSED Test "cortexm_fpu": PASSED Test "crc": PASSED Test "flash_physical": PASSED Test "flash_write_protect": PASSED Test "fpsensor_hw": PASSED Test "fpsensor_spi_ro": PASSED Test "fpsensor_spi_rw": PASSED Test "fpsensor_uart_ro": PASSED Test "fpsensor_uart_rw": PASSED Test "mpu_ro": PASSED Test "mpu_rw": PASSED Test "mutex": PASSED Test "pingpong": PASSED Test "printf": PASSED Test "queue": PASSED Test "rollback_region0": PASSED Test "rollback_region1": PASSED Test "rollback_entropy": PASSED Test "rtc": PASSED Test "sha256": PASSED Test "sha256_unrolled": PASSED Test "static_if": PASSED Test "stdlib": PASSED Test "system_is_locked_wp_on": PASSED Test "system_is_locked_wp_off": PASSED Test "timer_dos": PASSED Test "utils": PASSED Test "utils_str": PASSED Test "stm32f_rtc": PASSED Test "panic_data_bloonchipper_v2.0.4277": PASSED Test "panic_data_bloonchipper_v2.0.5938": PASSED Force-Relevant-Builds: all Signed-off-by: Tom Hughes <tomhughes@chromium.org> Change-Id: I264ad0ffe7afcd507a1e483c6e934a9c4fea47c3
Diffstat (limited to 'core/cortex-m/mpu.c')
-rw-r--r--core/cortex-m/mpu.c64
1 files changed, 28 insertions, 36 deletions
diff --git a/core/cortex-m/mpu.c b/core/cortex-m/mpu.c
index 29da931a28..c0793180dc 100644
--- a/core/cortex-m/mpu.c
+++ b/core/cortex-m/mpu.c
@@ -1,10 +1,11 @@
-/* Copyright 2013 The Chromium OS Authors. All rights reserved.
+/* Copyright 2013 The ChromiumOS Authors
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*/
/* MPU module for Chrome EC */
+#include "builtin/assert.h"
#include "mpu.h"
#include "console.h"
#include "cpu.h"
@@ -37,7 +38,6 @@ bool mpu_is_unified(void)
return (mpu_get_type() & MPU_TYPE_UNIFIED_MASK) == 0;
}
-
/**
* Update a memory region.
*
@@ -74,7 +74,7 @@ int mpu_update_region(uint8_t region, uint32_t addr, uint8_t size_bit,
asm volatile("isb; dsb;");
MPU_NUMBER = region;
- MPU_SIZE &= ~1; /* Disable */
+ MPU_SIZE &= ~1; /* Disable */
if (enable) {
MPU_BASE = addr;
/*
@@ -85,8 +85,8 @@ int mpu_update_region(uint8_t region, uint32_t addr, uint8_t size_bit,
* according to the doc, but they don't ..., do a single 32-bit
* one.
*/
- REG32(&MPU_SIZE) = ((uint32_t)attr << 16)
- | (srd << 8) | ((size_bit - 1) << 1) | 1;
+ REG32(&MPU_SIZE) = ((uint32_t)attr << 16) | (srd << 8) |
+ ((size_bit - 1) << 1) | 1;
}
asm volatile("isb; dsb;");
@@ -117,7 +117,7 @@ static int mpu_config_region_greedy(uint8_t region, uint32_t addr,
* regions must be naturally aligned to their size.
*/
uint8_t natural_alignment = MIN(addr == 0 ? 32 : alignment_log2(addr),
- alignment_log2(size));
+ alignment_log2(size));
uint8_t subregion_disable = 0;
if (natural_alignment >= 5) {
@@ -159,10 +159,9 @@ static int mpu_config_region_greedy(uint8_t region, uint32_t addr,
*consumed = 1 << natural_alignment;
}
- return mpu_update_region(region,
- addr & ~((1 << natural_alignment) - 1),
- natural_alignment,
- attr, enable, subregion_disable);
+ return mpu_update_region(region, addr & ~((1 << natural_alignment) - 1),
+ natural_alignment, attr, enable,
+ subregion_disable);
}
/**
@@ -188,8 +187,8 @@ int mpu_config_region(uint8_t region, uint32_t addr, uint32_t size,
if (size == 0)
return EC_SUCCESS;
- rv = mpu_config_region_greedy(region, addr, size,
- attr, enable, &consumed);
+ rv = mpu_config_region_greedy(region, addr, size, attr, enable,
+ &consumed);
if (rv != EC_SUCCESS)
return rv;
ASSERT(consumed <= size);
@@ -198,8 +197,8 @@ int mpu_config_region(uint8_t region, uint32_t addr, uint32_t size,
/* Regions other than DATA_RAM_TEXT may use two MPU regions */
if (size > 0 && region != REGION_DATA_RAM_TEXT) {
- rv = mpu_config_region_greedy(region + 1, addr, size,
- attr, enable, &consumed);
+ rv = mpu_config_region_greedy(region + 1, addr, size, attr,
+ enable, &consumed);
if (rv != EC_SUCCESS)
return rv;
ASSERT(consumed <= size);
@@ -223,8 +222,8 @@ int mpu_config_region(uint8_t region, uint32_t addr, uint32_t size,
static int mpu_unlock_region(uint8_t region, uint32_t addr, uint32_t size,
uint8_t texscb)
{
- return mpu_config_region(region, addr, size,
- MPU_ATTR_RW_RW | texscb, 1);
+ return mpu_config_region(region, addr, size, MPU_ATTR_RW_RW | texscb,
+ 1);
}
void mpu_enable(void)
@@ -247,13 +246,9 @@ int mpu_protect_data_ram(void)
int ret;
/* Prevent code execution from data RAM */
- ret = mpu_config_region(REGION_DATA_RAM,
- CONFIG_RAM_BASE,
- CONFIG_DATA_RAM_SIZE,
- MPU_ATTR_XN |
- MPU_ATTR_RW_RW |
- MPU_ATTR_INTERNAL_SRAM,
- 1);
+ ret = mpu_config_region(
+ REGION_DATA_RAM, CONFIG_RAM_BASE, CONFIG_DATA_RAM_SIZE,
+ MPU_ATTR_XN | MPU_ATTR_RW_RW | MPU_ATTR_INTERNAL_SRAM, 1);
if (ret != EC_SUCCESS)
return ret;
@@ -271,18 +266,16 @@ int mpu_protect_code_ram(void)
return mpu_config_region(REGION_STORAGE,
CONFIG_PROGRAM_MEMORY_BASE + CONFIG_RO_MEM_OFF,
CONFIG_CODE_RAM_SIZE,
- MPU_ATTR_RO_NO | MPU_ATTR_INTERNAL_SRAM,
- 1);
+ MPU_ATTR_RO_NO | MPU_ATTR_INTERNAL_SRAM, 1);
}
#else
int mpu_lock_ro_flash(void)
{
/* Prevent execution from internal mapped RO flash */
- return mpu_config_region(REGION_STORAGE,
- CONFIG_MAPPED_STORAGE_BASE + CONFIG_RO_MEM_OFF,
- CONFIG_RO_SIZE,
- MPU_ATTR_XN | MPU_ATTR_RW_RW |
- MPU_ATTR_FLASH_MEMORY, 1);
+ return mpu_config_region(
+ REGION_STORAGE, CONFIG_MAPPED_STORAGE_BASE + CONFIG_RO_MEM_OFF,
+ CONFIG_RO_SIZE,
+ MPU_ATTR_XN | MPU_ATTR_RW_RW | MPU_ATTR_FLASH_MEMORY, 1);
}
/* Represent RW with at most 2 MPU regions. */
@@ -298,8 +291,7 @@ struct mpu_rw_regions mpu_get_rw_regions(void)
* the region because on the Cortex-M3, Cortex-M4 and Cortex-M7, the
* address used for an MPU region must be aligned to the size.
*/
- aligned_size_bit =
- __fls(regions.addr[0] & -regions.addr[0]);
+ aligned_size_bit = __fls(regions.addr[0] & -regions.addr[0]);
regions.size[0] = MIN(BIT(aligned_size_bit), CONFIG_RW_SIZE);
regions.addr[1] = regions.addr[0] + regions.size[0];
regions.size[1] = CONFIG_RW_SIZE - regions.size[0];
@@ -386,10 +378,10 @@ int mpu_lock_rollback(int lock)
#ifdef CONFIG_CHIP_UNCACHED_REGION
/* Store temporarily the regions ranges to use them for the MPU configuration */
-#define REGION(_name, _flag, _start, _size) \
- static const uint32_t CONCAT2(_region_start_, _name) \
+#define REGION(_name, _flag, _start, _size) \
+ static const uint32_t CONCAT2(_region_start_, _name) \
__attribute__((unused, section(".unused"))) = _start; \
- static const uint32_t CONCAT2(_region_size_, _name) \
+ static const uint32_t CONCAT2(_region_size_, _name) \
__attribute__((unused, section(".unused"))) = _size;
#include "memory_regions.inc"
#undef REGION
@@ -424,7 +416,7 @@ int mpu_pre_init(void)
* to the region size.
*/
rv = mpu_update_region(i, CORTEX_M_SRAM_BASE, MPU_SIZE_BITS_MIN,
- 0, 0, 0);
+ 0, 0, 0);
if (rv != EC_SUCCESS)
return rv;
}