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| author | Vincent Palatin <vpalatin@chromium.org> | 2014-03-01 10:20:47 -0800 |
|---|---|---|
| committer | chrome-internal-fetch <chrome-internal-fetch@google.com> | 2014-03-11 05:52:41 +0000 |
| commit | 0f73a129b42acfcad843203b602fbbcc8894c614 (patch) | |
| tree | 9531fae7a8d9c3290973fe5b5ee47e57cd485546 /core/cortex-m0/atomic.h | |
| parent | 7aab81edce830e15134b52256ad3186e08951b10 (diff) | |
| download | chrome-ec-0f73a129b42acfcad843203b602fbbcc8894c614.tar.gz | |
Add Cortex-M0 core support
The Cortex-M0 core is based on ARMv6-M instruction set rather than
ARMv7-M as Cortex-M3 and M4.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=none
TEST=run console on STM32F072,
and pass all available unit-tests on target.
Change-Id: I9bdf6637132ba4a3e739d388580a72b4c84e930e
Reviewed-on: https://chromium-review.googlesource.com/188982
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Diffstat (limited to 'core/cortex-m0/atomic.h')
| -rw-r--r-- | core/cortex-m0/atomic.h | 64 |
1 files changed, 64 insertions, 0 deletions
diff --git a/core/cortex-m0/atomic.h b/core/cortex-m0/atomic.h new file mode 100644 index 0000000000..ca3d3d47ba --- /dev/null +++ b/core/cortex-m0/atomic.h @@ -0,0 +1,64 @@ +/* Copyright (c) 2014 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* Atomic operations for ARMv6-M */ + +#ifndef __CROS_EC_ATOMIC_H +#define __CROS_EC_ATOMIC_H + +#include "common.h" + +/** + * Implements atomic arithmetic operations on 32-bit integers. + * + * There is no load/store exclusive on ARMv6-M, just disable interrupts + */ +#define ATOMIC_OP(asm_op, a, v) do { \ + uint32_t reg0; \ + \ + __asm__ __volatile__(" cpsid i\n" \ + " ldr %0, [%1]\n" \ + #asm_op" %0, %0, %2\n" \ + " str %0, [%1]\n" \ + " cpsie i\n" \ + : "=&r" (reg0) \ + : "r" (a), "r" (v) : "cc"); \ +} while (0) + +static inline void atomic_clear(uint32_t *addr, uint32_t bits) +{ + ATOMIC_OP(bic, addr, bits); +} + +static inline void atomic_or(uint32_t *addr, uint32_t bits) +{ + ATOMIC_OP(orr, addr, bits); +} + +static inline void atomic_add(uint32_t *addr, uint32_t value) +{ + ATOMIC_OP(add, addr, value); +} + +static inline void atomic_sub(uint32_t *addr, uint32_t value) +{ + ATOMIC_OP(sub, addr, value); +} + +static inline uint32_t atomic_read_clear(uint32_t *addr) +{ + uint32_t ret; + + __asm__ __volatile__(" mov %2, #0\n" + " cpsid i\n" + " ldr %0, [%1]\n" + " str %2, [%1]\n" + " cpsie i\n" + : "=&r" (ret) + : "r" (addr), "r" (0) : "cc"); + + return ret; +} +#endif /* __CROS_EC_ATOMIC_H */ |