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| author | Vincent Palatin <vpalatin@chromium.org> | 2018-03-02 11:17:11 +0100 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2018-03-05 23:48:28 -0800 |
| commit | b42dd73603844c03b44d88a4513df330ee168496 (patch) | |
| tree | 3fc605851bb6049e59fe44676c62c26db6e4a8fd /core/cortex-m0/ec.lds.S | |
| parent | 6d567bc45ffcc3b8df2c288f8347d00a250248fc (diff) | |
| download | chrome-ec-b42dd73603844c03b44d88a4513df330ee168496.tar.gz | |
core: add chip-specific memory regions definition mechanism
When a chip has special/non-contiguous SRAM physical memory region,
rather than extending the generic linker file ad nauseam, define a
mechanism to declare a chip specific list of those regions.
To do so, a chip must declare the CONFIG_CHIP_MEMORY_REGIONS
configuration and have a memory_regions.inc with the list of regions.
The special-purpose preprocessed chip/<chip_name>/memory_regions.inc
file has one region declaration per line using the following macro:
REGION(name, attributes, start_address, size)
Each region will get a proper MEMORY entry and a section in the linker
file.
the __SECTION(region_name) helper is provided as a convenience to
declare variable in a specific region.
Note: those 'special' regions are NOT cleared at startup contrary to
.bss.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=b:67081508
TEST=on ZerbleBarn, along with the following CLs, run the firmware with
large arrays in special AHB memory regions.
Change-Id: I3f156ef6e5feb4a6a0b2ae2468bae8a20483f17c
Reviewed-on: https://chromium-review.googlesource.com/946368
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Diffstat (limited to 'core/cortex-m0/ec.lds.S')
| -rw-r--r-- | core/cortex-m0/ec.lds.S | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/core/cortex-m0/ec.lds.S b/core/cortex-m0/ec.lds.S index ce4ef3849d..ce1bcdbc70 100644 --- a/core/cortex-m0/ec.lds.S +++ b/core/cortex-m0/ec.lds.S @@ -30,6 +30,12 @@ MEMORY ORIGIN = CONFIG_USB_RAM_BASE, \ LENGTH = CONFIG_USB_RAM_SIZE * CONFIG_USB_RAM_ACCESS_SIZE / 2 #endif +#ifdef CONFIG_CHIP_MEMORY_REGIONS +#define REGION(name, attr, start, size) \ + name(attr) : ORIGIN = (start), LENGTH = (size) +#include "memory_regions.inc" +#undef REGION +#endif /* CONFIG_MEMORY_REGIONS */ } SECTIONS { @@ -248,6 +254,16 @@ SECTIONS *(.usb_ram.data) } > USB_RAM #endif +#ifdef CONFIG_CHIP_MEMORY_REGIONS +#define REGION(name, attr, start, size) \ + .name(NOLOAD) : { \ + __##name##_start = .; \ + *(SORT(.name.*)) \ + } > name +#include "memory_regions.inc" +#undef REGION +#endif /* CONFIG_CHIP_MEMORY_REGIONS */ + #if !(defined(SECTION_IS_RO) && defined(CONFIG_FLASH)) /DISCARD/ : { *(.google) |