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| author | Bill Richardson <wfrichar@chromium.org> | 2015-07-09 13:42:52 -0700 |
|---|---|---|
| committer | ChromeOS Commit Bot <chromeos-commit-bot@chromium.org> | 2015-07-13 18:43:50 +0000 |
| commit | 41b538d4c6df5311fbf76495c187a4781938ae49 (patch) | |
| tree | 23274def05ff1a3e7a8d8bd9bc447538ad6645e8 /core/cortex-m0/task.c | |
| parent | 4c708232ac82e2c0bfe075027fbe88afd9456535 (diff) | |
| download | chrome-ec-41b538d4c6df5311fbf76495c187a4781938ae49.tar.gz | |
Cr50: Pass SPI and SPS modes to sps_register_rx_handler()
This lets the RX interrupt handler configure the wire protocol
(clock polarity and phase) and SPS communication mode that it
would prefer.
BUG=chrome-os-partner:40969
BRANCH=none
TEST=make buildall
This is just a refactoring, since the sps_hc.c module is the only
thing that uses this (in one mode only). I tested it using
extra/ftdi_hostcmd and it still works.
Change-Id: I9ed26e9fa66de65e72f188184f4f3f41a5b5562a
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/284922
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Diffstat (limited to 'core/cortex-m0/task.c')
0 files changed, 0 insertions, 0 deletions