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| author | Philip Chen <philipchen@google.com> | 2017-12-01 11:16:58 -0800 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2017-12-11 15:16:23 -0800 |
| commit | 0037fb8dfcd7136d40e608ad9973331bd82d9a80 (patch) | |
| tree | 15677d4993958e2b173675411933f565fead2ff7 /core/cortex-m0 | |
| parent | 665ee232999ab22a9e0a53ddba020e0b1f387fcf (diff) | |
| download | chrome-ec-0037fb8dfcd7136d40e608ad9973331bd82d9a80.tar.gz | |
system: Log PC and task id on watchdog
For debug, in common code let's log the watchdog PC
and task id as our SW panic params.
BUG=chromium:790006
BRANCH=none
TEST=manually test scarlet rev2 from a1-a3, b1-b2:
(a1) Add 'while(1);' in button ISR
(a2) Boot and press the button
(a3) When watchdog is triggeried, check with 'panicinfo'
that saved R5 is the PC for button ISR.
(b1) 'crash watchdog' in EC console
(b2) Check with 'panicinfo' that CONSOLE task id is saved in
EXCEPTION and PC is saved in R5.
Change-Id: I64d2fcf594dd24b0951e002ab8e80ebcac2d1def
Signed-off-by: Philip Chen <philipchen@google.com>
Reviewed-on: https://chromium-review.googlesource.com/803618
Commit-Ready: Philip Chen <philipchen@chromium.org>
Tested-by: Philip Chen <philipchen@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Diffstat (limited to 'core/cortex-m0')
| -rw-r--r-- | core/cortex-m0/watchdog.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/core/cortex-m0/watchdog.c b/core/cortex-m0/watchdog.c index a4e34d51bf..3d53b4979c 100644 --- a/core/cortex-m0/watchdog.c +++ b/core/cortex-m0/watchdog.c @@ -25,6 +25,10 @@ void watchdog_trace(uint32_t excep_lr, uint32_t excep_sp) stack = (uint32_t *)psp; } + /* Log PC. If we were in task context, log task id too. */ + panic_set_reason(PANIC_SW_WATCHDOG, stack[6], + (excep_lr & 0xf) == 1 ? 0xff : task_get_current()); + panic_printf("### WATCHDOG PC=%08x / LR=%08x / pSP=%08x ", stack[6], stack[5], psp); if ((excep_lr & 0xf) == 1) |