diff options
| author | Vincent Palatin <vpalatin@chromium.org> | 2015-04-27 14:47:19 -0700 |
|---|---|---|
| committer | ChromeOS Commit Bot <chromeos-commit-bot@chromium.org> | 2015-05-19 02:46:27 +0000 |
| commit | 2650ff3d70c9933e4c3dcd1401ca66b4426def4a (patch) | |
| tree | 7a4658b060d3439a525a7562c226358d55424035 /core/cortex-m0 | |
| parent | cb29daa58c0fa5866a7847c454967ef0376c7688 (diff) | |
| download | chrome-ec-2650ff3d70c9933e4c3dcd1401ca66b4426def4a.tar.gz | |
Add option to enable GCC LTO
Add CONFIG_LTO to use GCC Link-Time Optimizations to try to reduce the
flash footprint of the firmware.
Add additional protection to some functions/data to avoid removal by the
linker when their usage is not obvious.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=none
TEST=make buildall (with and without LTO enable on all boards)
Change-Id: I586b8c1eda4592b416c85383b65153c1d5ab0059
Reviewed-on: https://chromium-review.googlesource.com/271291
Trybot-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
Diffstat (limited to 'core/cortex-m0')
| -rw-r--r-- | core/cortex-m0/atomic.h | 2 | ||||
| -rw-r--r-- | core/cortex-m0/build.mk | 5 | ||||
| -rw-r--r-- | core/cortex-m0/panic.c | 4 | ||||
| -rw-r--r-- | core/cortex-m0/task.c | 2 |
4 files changed, 9 insertions, 4 deletions
diff --git a/core/cortex-m0/atomic.h b/core/cortex-m0/atomic.h index 8ba1b66739..62bc2ff370 100644 --- a/core/cortex-m0/atomic.h +++ b/core/cortex-m0/atomic.h @@ -23,7 +23,7 @@ #asm_op" %0, %0, %2\n" \ " str %0, [%1]\n" \ " cpsie i\n" \ - : "=&r" (reg0) \ + : "=&b" (reg0) \ : "b" (a), "r" (v) : "cc"); \ } while (0) diff --git a/core/cortex-m0/build.mk b/core/cortex-m0/build.mk index c87df856e0..5f2bc32eb5 100644 --- a/core/cortex-m0/build.mk +++ b/core/cortex-m0/build.mk @@ -13,6 +13,11 @@ CROSS_COMPILE?=arm-none-eabi- CFLAGS_CPU+=-mthumb -Os -mno-sched-prolog CFLAGS_CPU+=-mno-unaligned-access +ifneq ($(CONFIG_LTO),) +CFLAGS_CPU+=-flto +LDFLAGS_EXTRA+=-flto +endif + core-y=cpu.o init.o thumb_case.o div.o lmul.o ldivmod.o uldivmod.o core-$(CONFIG_COMMON_PANIC_OUTPUT)+=panic.o core-$(CONFIG_COMMON_RUNTIME)+=switch.o task.o diff --git a/core/cortex-m0/panic.c b/core/cortex-m0/panic.c index 2ba22c6998..cb347054ea 100644 --- a/core/cortex-m0/panic.c +++ b/core/cortex-m0/panic.c @@ -104,7 +104,7 @@ void panic_data_print(const struct panic_data *pdata) print_reg(15, sregs, 6); } -void report_panic(void) +void __keep report_panic(void) { struct panic_data *pdata = pdata_ptr; uint32_t sp; @@ -139,7 +139,7 @@ void report_panic(void) * * Declare this as a naked call so we can extract raw LR and IPSR values. */ -void exception_panic(void) __attribute__((naked)); +__keep void exception_panic(void) __attribute__((naked)); void exception_panic(void) { /* Save registers and branch directly to panic handler */ diff --git a/core/cortex-m0/task.c b/core/cortex-m0/task.c index ffdbe49595..d26a82b6d2 100644 --- a/core/cortex-m0/task.c +++ b/core/cortex-m0/task.c @@ -181,7 +181,7 @@ int task_start_called(void) /** * Scheduling system call */ -task_ *__svc_handler(int desched, task_id_t resched) +task_ __attribute__((noinline)) *__svc_handler(int desched, task_id_t resched) { task_ *current, *next; #ifdef CONFIG_TASK_PROFILING |