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authorShawn Nematbakhsh <shawnn@chromium.org>2015-09-04 19:09:33 -0700
committerchrome-bot <chrome-bot@chromium.org>2015-09-16 14:49:31 -0700
commitd58e54730c03290296df5bb65cb84264e4b2facc (patch)
treed736570c84a0e9737b8881ec68b073327a5c2ae5 /core/cortex-m0
parent4b3c13ddfefd229dde49fb4cbf5a6bfc49f64973 (diff)
downloadchrome-ec-d58e54730c03290296df5bb65cb84264e4b2facc.tar.gz
cleanup: Rename geometry constants
Rename and add geometry constants to match spec doc - https://goo.gl/fnzTvr. CONFIG_FLASH_BASE becomes CONFIG_PROGRAM_MEMORY_BASE CONFIG_FLASH_MAPPED becomes CONFIG_MAPPED_STORAGE Add CONFIG_INTERNAL_STORAGE, CONFIG_EXTERNAL_STORAGE and CONFIG_MAPPED_STORAGE_BASE where appropriate. This CL leaves chip/npcx in a broken state -- it's fixed in a follow-up CL. BRANCH=None BUG=chrome-os-partner:23796 TEST=With entire patch series, on both Samus and Glados: - Verify 'version' EC console command is correct - Verify 'flashrom -p ec -r read.bin' reads back EC image - Verify software sync correctly flashes both EC and PD RW images Change-Id: Idb3c4ed9f7f6edd0a6d49ad11753eba713e67a80 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/297484 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
Diffstat (limited to 'core/cortex-m0')
-rw-r--r--core/cortex-m0/ec.lds.S2
1 files changed, 1 insertions, 1 deletions
diff --git a/core/cortex-m0/ec.lds.S b/core/cortex-m0/ec.lds.S
index 8f3f382c98..629046ed0b 100644
--- a/core/cortex-m0/ec.lds.S
+++ b/core/cortex-m0/ec.lds.S
@@ -6,7 +6,7 @@
#include "rsa.h"
#define FW_OFF_(section) CONFIG_##section##_MEM_OFF
-#define FW_OFF(section) (CONFIG_FLASH_BASE + FW_OFF_(section))
+#define FW_OFF(section) (CONFIG_PROGRAM_MEMORY_BASE + FW_OFF_(section))
#define FW_SIZE_(section) CONFIG_##section##_SIZE
#define FW_SIZE(section) FW_SIZE_(section)