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| author | Peter Marheine <pmarheine@chromium.org> | 2021-02-15 15:09:02 +1100 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2021-02-18 00:20:48 +0000 |
| commit | b9588a7499d15e4539720ec87624351a68011337 (patch) | |
| tree | 93dd42f1a67f02e2f74f6f20aa6391c120b8d5b6 /core/cortex-m0 | |
| parent | c0efec9de427981f9c971cad7264f11caf780f6f (diff) | |
| download | chrome-ec-b9588a7499d15e4539720ec87624351a68011337.tar.gz | |
cortex-m0: convert "b" register constraints to "l"
GCC defines the "b" constraint for ARM targets as the union of the stack
register and low registers (r0-r7), but that constraint is marked as
internal (not intended for general use) and is not supported by Clang.
Instead use "l" (the low registers only), which is intended for general
use and supported by clang.
BUG=b:172221010
TEST=builds
BRANCH=None
Signed-off-by: Peter Marheine <pmarheine@chromium.org>
Change-Id: I584274b2aa1c68dfdfef80de779191d1f4d0e7b2
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2695054
Reviewed-by: Abe Levkoy <alevkoy@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Diffstat (limited to 'core/cortex-m0')
| -rw-r--r-- | core/cortex-m0/atomic.h | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/core/cortex-m0/atomic.h b/core/cortex-m0/atomic.h index 79924fa234..e969f01de1 100644 --- a/core/cortex-m0/atomic.h +++ b/core/cortex-m0/atomic.h @@ -28,8 +28,8 @@ typedef atomic_t atomic_val_t; #asm_op" %0, %0, %3\n" \ " str %0, [%2]\n" \ " cpsie i\n" \ - : "=&b"(reg0), "=&b"(reg1) \ - : "b"(a), "r"(v) \ + : "=&l"(reg0), "=&l"(reg1) \ + : "l"(a), "r"(v) \ : "cc", "memory"); \ reg1; \ }) @@ -63,8 +63,8 @@ static inline atomic_val_t atomic_clear(atomic_t *addr) " ldr %0, [%1]\n" " str %2, [%1]\n" " cpsie i\n" - : "=&b" (ret) - : "b" (addr), "r" (0) + : "=&l" (ret) + : "l" (addr), "r" (0) : "cc", "memory"); return ret; |