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| author | Kyoung Kim <kyoung.il.kim@intel.com> | 2015-03-23 18:18:36 -0700 |
|---|---|---|
| committer | ChromeOS Commit Bot <chromeos-commit-bot@chromium.org> | 2015-07-17 18:09:55 +0000 |
| commit | 0e53f9d425e9a5bdad084b231438b7ec87432f3a (patch) | |
| tree | 43c25ac86f19de0c0d1f812c2052b4e61fbbb456 /core/cortex-m | |
| parent | 2e9ab7cbe48934deab914d96feb9141fdae95197 (diff) | |
| download | chrome-ec-0e53f9d425e9a5bdad084b231438b7ec87432f3a.tar.gz | |
mec1322: heavysleep in idle task and console deepsleep
Implemented mec1322's heavysleep in idle task to
reduce further EC power down on S3.
MEC1322 needs sleep-enabled for all blocks to
acheive max power down including UART.
Real heavysleep will be effective only when
console/uart is not active.
To enable this commit, board-specific commit is required.
For example, check commit, "Enabling heavysleep idle task at S3".
Test:
1. Put device into S3 mode by typing 'powerd_dbus_suspend" in Linux
shell.
2. wait at least 1 min till EC console sleeps
3. measure EC power.
Since idle task is continuously scheduled, EC will enters/exits
to/from heavy sleep mode frequently in S3 and power consumption
will be changed dynamically.
For acurate power measurement, high-sampling-rate measurement
system might be required and using DMM might not give accurate
number.
BUG=None
TEST=Tested on evt1p0/evt1p7/DVT
BRANCH=None
Change-Id: I435ca347cab2f4d51cefeee802c3bf30fb393fa1
Signed-off-by: Kyoung Kim <kyoung.il.kim@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/283603
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Tested-by: Alec Berg <alecaberg@chromium.org>
Commit-Queue: Alec Berg <alecaberg@chromium.org>
Diffstat (limited to 'core/cortex-m')
| -rw-r--r-- | core/cortex-m/cpu.h | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/core/cortex-m/cpu.h b/core/cortex-m/cpu.h index e170d42782..2951f4b5e0 100644 --- a/core/cortex-m/cpu.h +++ b/core/cortex-m/cpu.h @@ -13,6 +13,12 @@ /* Macro to access 32-bit registers */ #define CPUREG(addr) (*(volatile uint32_t*)(addr)) +#define CPU_NVIC_ST_CTRL CPUREG(0xE000E010) +#define ST_ENABLE (1 << 0) +#define ST_TICKINT (1 << 1) +#define ST_CLKSOURCE (1 << 2) +#define ST_COUNTFLAG (1 << 16) + /* Nested Vectored Interrupt Controller */ #define CPU_NVIC_EN(x) CPUREG(0xe000e100 + 4 * (x)) #define CPU_NVIC_DIS(x) CPUREG(0xe000e180 + 4 * (x)) |