diff options
| author | Ian Chao <mlchao@nuvoton.com> | 2015-06-25 18:12:09 +0800 |
|---|---|---|
| committer | ChromeOS Commit Bot <chromeos-commit-bot@chromium.org> | 2015-06-26 18:57:32 +0000 |
| commit | 957638c78cc5aa0ba37ef281e2c6a09215c5d60e (patch) | |
| tree | bc783f701e5b968449bfe3652e8cc20680620c8d /core/cortex-m | |
| parent | ccb6b15d514b695b9ea472aa98d5f1730d58e244 (diff) | |
| download | chrome-ec-957638c78cc5aa0ba37ef281e2c6a09215c5d60e.tar.gz | |
nuc: Add SHI driver for arm-based platform in chip folder.
Add npcx_evb_arm board-level driver for arm-based platform.
Add header.c: for booting from NPCX5M5G A3 Booter.
Remove lfw folder due to those functionalitie have been replaced with Booter
Modified drivers for
Patch Set 1:
1. flash.c: Implement UMA lock, tri-state and selection register lock functionalities
2. hwtimer.c: Add ITIM32 for hwtimer
3. lpc.c: Add checking for LRESET
4. system.c: Modified CODERAM_ARCH functions for NPCX5M5G A3 Booter.
5. uart.c: Add support for module 2
Patch Set 2:
6. lpc.c: Modified lpc_get_pltrst_asserted() func
Patch Set 3:
7. minimize the changes for CONFIG_CODERAM_ARCH in common layer
8. comments of Patch Set1/2
Patch Set 4:
9. Modified CONFIG_RO_MEM_OFF point to ro image and keep header as a part of ec.RO.flat.
10. Fixed RO_FRID and RW_FRID issues which caused by CONFIG_CODERAM_ARCH.
Patch Set 5:
11. Modified system.c in common folder for supporting *_STORAGE_OFF.
12. Use *_STORAGE_OFF in firmware_image.lds.S to indicate flat file layout in flash.
Patch Set 6:
13. rebase to newest version
14. system.c: Modified for the newest include/system.h
Patch Set 7:
15. Merge from version 0625
BUG=chrome-os-partner:34346
TEST=make buildall -j; test nuvoton IC specific drivers
BRANCH=none
Change-Id: Ifd7c10b81b5781ccd75bb2558dc236486976e8ed
Signed-off-by: Ian Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/272034
Reviewed-by: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Commit-Queue: Shawn N <shawnn@chromium.org>
Diffstat (limited to 'core/cortex-m')
| -rw-r--r-- | core/cortex-m/ec.lds.S | 19 |
1 files changed, 16 insertions, 3 deletions
diff --git a/core/cortex-m/ec.lds.S b/core/cortex-m/ec.lds.S index df3898e255..d637860329 100644 --- a/core/cortex-m/ec.lds.S +++ b/core/cortex-m/ec.lds.S @@ -18,6 +18,15 @@ OUTPUT_ARCH(BFD_ARCH) ENTRY(reset) MEMORY { +#if defined(SECTION_IS_RO) && defined(NPCX_RO_HEADER) + /* + * Header structure used by npcx booter in RO region. + * Please notice the location of header must be in front of FW + * which needs copy. But header itself won't be copied to code ram + * by booter. + */ + FLASH_HDR (rx) : ORIGIN = FW_OFF(RO_HDR), LENGTH = FW_SIZE(RO_HDR) +#endif FLASH (rx) : ORIGIN = FW_OFF(SECTION), LENGTH = FW_SIZE(SECTION) IRAM (rw) : ORIGIN = CONFIG_RAM_BASE, LENGTH = CONFIG_RAM_SIZE #ifdef CONFIG_CODERAM_ARCH @@ -45,6 +54,11 @@ MEMORY } SECTIONS { +#if defined(SECTION_IS_RO) && defined(NPCX_RO_HEADER) + .header : { + KEEP(*(.header)) + } > FLASH_HDR +#endif .text : { OUTDIR/core/CORE/init.o (.text.vecttable) . = ALIGN(4); @@ -66,7 +80,7 @@ SECTIONS /* Entering deep idle FW for better power consumption */ KEEP(*(.lowpower_ram)) __flash_lpfw_end = .; - } > CDRAM AT > FLASH + } > CDRAM AT > FLASH #else #ifdef COMPILE_FOR_RAM } > IRAM @@ -182,7 +196,7 @@ SECTIONS #endif . = ALIGN(4); #ifdef CONFIG_CODERAM_ARCH - } > CDRAM AT > FLASH + } > CDRAM AT > FLASH #else #ifdef COMPILE_FOR_RAM } > IRAM @@ -219,7 +233,6 @@ SECTIONS .data : { #else #ifdef CONFIG_CODERAM_ARCH - __data_start = . ; .data : AT(LOADADDR(.rodata) + SIZEOF(.rodata)) { #else .data : AT(ADDR(.rodata) + SIZEOF(.rodata)) { |