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| author | Shawn Nematbakhsh <shawnn@chromium.org> | 2015-06-04 11:19:00 -0700 |
|---|---|---|
| committer | ChromeOS Commit Bot <chromeos-commit-bot@chromium.org> | 2015-06-13 07:12:38 +0000 |
| commit | 5ea69a7b3b06d8877fc0d420a6892b1db42cd290 (patch) | |
| tree | ffe0acc47e636994108d71a9777c299c545490ff /core/cortex-m | |
| parent | 1dfd58daf6d5a1d1452e7ce8f164b1e07c995d45 (diff) | |
| download | chrome-ec-5ea69a7b3b06d8877fc0d420a6892b1db42cd290.tar.gz | |
coderam: Don't assume that RO/RW images reside at start of code memory
RO/RW images may reside at an offset to the start of code memory,
defined at the chip-level by CONFIG_R*_MEM_OFF.
BUG=chrome-os-partner:38103
TEST=Manual on Cyan. Verify sysjump works correctly in both directions.
BRANCH=None
Change-Id: I54c5f20335a5646d49afcc8d3fa2eb90ca9349d0
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/274434
Reviewed-by: Divya Jyothi <divya.jyothi@intel.com>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Tested-by: Divya Jyothi <divya.jyothi@intel.com>
Reviewed-by: Mulin Chao <mlchao@nuvoton.com>
Tested-by: Mulin Chao <mlchao@nuvoton.com>
Diffstat (limited to 'core/cortex-m')
| -rw-r--r-- | core/cortex-m/ec.lds.S | 23 |
1 files changed, 17 insertions, 6 deletions
diff --git a/core/cortex-m/ec.lds.S b/core/cortex-m/ec.lds.S index 4078b85445..df3898e255 100644 --- a/core/cortex-m/ec.lds.S +++ b/core/cortex-m/ec.lds.S @@ -5,8 +5,9 @@ #include "config.h" #include "rsa.h" -#define FW_OFF_(section) CONFIG_##section##_MEM_OFF -#define FW_OFF(section) (CONFIG_FLASH_BASE + FW_OFF_(section)) +#define FW_MEM_OFF_(section) CONFIG_##section##_MEM_OFF +#define FW_MEM_OFF(section) (FW_MEM_OFF_(section)) +#define FW_OFF(section) (CONFIG_FLASH_BASE + FW_MEM_OFF(section)) #define FW_SIZE_(section) CONFIG_##section##_SIZE #define FW_SIZE(section) FW_SIZE_(section) @@ -20,11 +21,21 @@ MEMORY FLASH (rx) : ORIGIN = FW_OFF(SECTION), LENGTH = FW_SIZE(SECTION) IRAM (rw) : ORIGIN = CONFIG_RAM_BASE, LENGTH = CONFIG_RAM_SIZE #ifdef CONFIG_CODERAM_ARCH - CDRAM (rx) : ORIGIN = CONFIG_CDRAM_BASE, LENGTH = CONFIG_CDRAM_SIZE -#endif +#ifdef CONFIG_FLASH_MAPPED + /* Geometry constants have non-standard meaning for npcx */ + CDRAM (rx) : \ + ORIGIN = CONFIG_CDRAM_BASE, \ + LENGTH = CONFIG_CDRAM_SIZE +#else /* CONFIG_FLASH_MAPPED */ + CDRAM (rx) : \ + ORIGIN = CONFIG_CDRAM_BASE + FW_MEM_OFF(SECTION), \ + LENGTH = FW_SIZE(SECTION) +#endif /* CONFIG_FLASH_MAPPED */ +#endif /* CONFIG_CODERAM_ARCH */ #ifdef RSA_PUBLIC_KEY_SIZE - PSTATE(r) : ORIGIN = FW_OFF(SECTION) + FW_SIZE(SECTION), \ - LENGTH = CONFIG_FW_PSTATE_SIZE + PSTATE(r) : \ + ORIGIN = FW_OFF(SECTION) + FW_SIZE(SECTION), \ + LENGTH = CONFIG_FW_PSTATE_SIZE #endif #ifdef CONFIG_USB_RAM_SIZE USB_RAM (rw) : \ |