diff options
author | Vincent Palatin <vpalatin@chromium.org> | 2018-01-30 17:01:50 +0100 |
---|---|---|
committer | chrome-bot <chrome-bot@chromium.org> | 2018-02-09 05:24:47 -0800 |
commit | 730491df202e5b14e489a5ab31a78e47fcd47af3 (patch) | |
tree | 3bf2d703861c832769ded44e18b42df614050356 /core/cortex-m | |
parent | 4ee04e1c4a978b49e5340e475e3db185e78e4949 (diff) | |
download | chrome-ec-730491df202e5b14e489a5ab31a78e47fcd47af3.tar.gz |
stm32: add internal flash support for STM32H7 family
The STM32H7 family has 2 banks of flash (with 2 hardware controllers
able to do 2 parallel operations at the same time).
Each bank of flash has 4 or 8 128-kB erase blocks (1MB and 2MB
variants).
The flash can only be written by 256-bit word (with an additional 10-bit
ECC computed by the hardware).
For the flash write-protection, we cannot use our 'classical' PSTATE
scheme as the erase-blocks are too large (128-kB) to dedicate one to
this and the embedded word in the RO partition would not work as the
flash has ECC and triggers bus-fault when the ECC is incorrect (which
includes the case where the 256-bit word is written a second time).
So we will do the following:
- use the RSS1 bit in the option bytes as the Write-Protect enabled bit.
- if the WP GPIO is set, lock at startup the option bytes until next
reboot.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=b:67081508
TEST=run flashinfo/flashwp/flashwrite/flasherase commands on the EC
console.
Change-Id: I823fce3bd42b4df212cf0b8ceceaca84109b78e6
Reviewed-on: https://chromium-review.googlesource.com/901423
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
Diffstat (limited to 'core/cortex-m')
-rw-r--r-- | core/cortex-m/panic.c | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/core/cortex-m/panic.c b/core/cortex-m/panic.c index 24174cfb2d..703586c135 100644 --- a/core/cortex-m/panic.c +++ b/core/cortex-m/panic.c @@ -425,5 +425,10 @@ void bus_fault_handler(void) void ignore_bus_fault(int ignored) { + /* + * Flash code might call this before cpu_init(), + * ensure that the bus faults really go through our handler. + */ + CPU_NVIC_SHCSR |= CPU_NVIC_SHCSR_BUSFAULTENA; bus_fault_ignored = ignored; } |