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| author | Jaiber John <jaiber.j.john@intel.com> | 2016-03-31 23:34:34 +0530 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2016-08-10 20:07:36 -0700 |
| commit | a625b710c3e4d64a659ae20682b85dd552657b6c (patch) | |
| tree | 88099f69bde18a59b4647e0fa1c0f09136ddb0cf /core/minute-ia/atomic.h | |
| parent | d54387c18e20f5973ae62fdc7f8a95872b52f4f5 (diff) | |
| download | chrome-ec-a625b710c3e4d64a659ae20682b85dd552657b6c.tar.gz | |
minute-ia: Enable x86 core for Intel ISH
Add intial minute-IA (x86) core to to enable the FW
to boot on Intel Integrated Sensor Hub (ISH).
BUG=chrome-os-partner:51851
BRANCH=None
TEST=`make buildall -j`
Change-Id: I4dcf841766f216cd00fb1d4214fae19ba5de5603
Signed-off-by: Jaiber John <jaiber.j.john@intel.com>
Signed-off-by: Alex Brill <alexander.brill@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/336443
Commit-Ready: Raj Mojumder <raj.mojumder@intel.com>
Tested-by: Raj Mojumder <raj.mojumder@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'core/minute-ia/atomic.h')
| -rw-r--r-- | core/minute-ia/atomic.h | 33 |
1 files changed, 33 insertions, 0 deletions
diff --git a/core/minute-ia/atomic.h b/core/minute-ia/atomic.h new file mode 100644 index 0000000000..4778c9aee9 --- /dev/null +++ b/core/minute-ia/atomic.h @@ -0,0 +1,33 @@ +/* Copyright (c) 2016 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* Atomic operations for x86 */ + +#ifndef __CROS_EC_ATOMIC_H +#define __CROS_EC_ATOMIC_H + +#include "common.h" +#include "util.h" + +#define ATOMIC_OP(asm_op, a, v) do { \ + __asm__ __volatile__ ( \ + "lock;" #asm_op " %0, %1\n" \ + : \ + : "r" (v), "m" (*a) \ + : "memory"); \ +} while (0) + +inline int bool_compare_and_swap_u32(uint32_t *var, uint32_t old_value, + uint32_t new_value); +inline void atomic_or_u8(uint8_t *var, uint8_t value); +inline void atomic_and_u8(uint8_t *var, uint8_t value); +inline void atomic_clear(uint32_t volatile *addr, uint32_t bits); +inline void atomic_or(uint32_t volatile *addr, uint32_t bits); +inline void atomic_add(uint32_t volatile *addr, uint32_t value); +inline void atomic_and(uint32_t volatile *addr, uint32_t value); +inline void atomic_sub(uint32_t volatile *addr, uint32_t value); +inline uint32_t atomic_read_clear(uint32_t volatile *addr); + +#endif /* __CROS_EC_ATOMIC_H */ |