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| author | Jack Rosenthal <jrosenth@chromium.org> | 2019-03-14 13:14:15 -0600 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2019-03-26 04:44:00 -0700 |
| commit | 9a5a7225737051e9523a775ebf8bba63f144259b (patch) | |
| tree | 4c604846f721c564c9dd966d7e5184230805c243 /core/minute-ia/interrupts.c | |
| parent | 5555323902f965a6e489e797f0e156d460e62d67 (diff) | |
| download | chrome-ec-9a5a7225737051e9523a775ebf8bba63f144259b.tar.gz | |
ish: Add watchdog timer
This adds support for the watchdog timer (WDT) available on Intel Sensor
Hub (ISH). The ISH will reset after T1 expires; see the comments at the
top of watchdog.c for further information on this design decision.
Originally, we had planned to implement a counter that would disable the
WDT after N failures. This was abandoned, since the register used to
store the counter was not able to maintain a value across reset on a
reliable basis (see b:128679825).
BUG=b:127980538,b:128679825
BRANCH=none
TEST=Used waitms command on arcada to verify WDT triggered a warning
IRQ after T1 and reset the system.
Change-Id: I4bd16c253110d60c57eb24cda2abc0facee20748
Signed-off-by: Jack Rosenthal <jrosenth@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1526316
Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com>
Reviewed-by: Jett Rink <jettrink@chromium.org>
Diffstat (limited to 'core/minute-ia/interrupts.c')
| -rw-r--r-- | core/minute-ia/interrupts.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/core/minute-ia/interrupts.c b/core/minute-ia/interrupts.c index 98c6c3509d..dab6ab5e99 100644 --- a/core/minute-ia/interrupts.c +++ b/core/minute-ia/interrupts.c @@ -91,6 +91,7 @@ static const irq_desc_t system_irqs[] = { LEVEL_INTR(ISH_I2C0_IRQ, ISH_I2C0_VEC), LEVEL_INTR(ISH_I2C1_IRQ, ISH_I2C1_VEC), LEVEL_INTR(ISH_I2C2_IRQ, ISH_I2C2_VEC), + LEVEL_INTR(ISH_WDT_IRQ, ISH_WDT_VEC), LEVEL_INTR(ISH_GPIO_IRQ, ISH_GPIO_VEC), LEVEL_INTR(ISH_IPC_HOST2ISH_IRQ, ISH_IPC_VEC), LEVEL_INTR(ISH_IPC_ISH2HOST_CLR_IRQ, ISH_IPC_ISH2HOST_CLR_VEC), |