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| author | Vincent Palatin <vpalatin@chromium.org> | 2013-10-25 15:37:11 -0700 |
|---|---|---|
| committer | chrome-internal-fetch <chrome-internal-fetch@google.com> | 2013-12-10 19:17:54 +0000 |
| commit | 93cc00fde1ba15c1f995fe963f30c9caecb02f77 (patch) | |
| tree | abd1b6d512e3e94a1e72aac2a83b2a03d7e4b5cb /core/nds32/atomic.h | |
| parent | 6f348ecf083a3182b7eed83cdd9a9bc19751a0ba (diff) | |
| download | chrome-ec-93cc00fde1ba15c1f995fe963f30c9caecb02f77.tar.gz | |
ite: Port OS layer to Andestar v3m architecture
This will be used to support ITE IT8380 chip which contains an Andes
N801 core.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=chrome-os-partner:23574
TEST=make BOARD=it8380dev
Change-Id: I91f9380c51c7712aa6a6418223a11551ab0091ce
Reviewed-on: https://chromium-review.googlesource.com/175480
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Diffstat (limited to 'core/nds32/atomic.h')
| -rw-r--r-- | core/nds32/atomic.h | 56 |
1 files changed, 56 insertions, 0 deletions
diff --git a/core/nds32/atomic.h b/core/nds32/atomic.h new file mode 100644 index 0000000000..3214067c43 --- /dev/null +++ b/core/nds32/atomic.h @@ -0,0 +1,56 @@ +/* Copyright (c) 2013 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* Atomic operations for Andes */ + +#ifndef __CROS_EC_ATOMIC_H +#define __CROS_EC_ATOMIC_H + +#include "common.h" +#include "cpu.h" + +static inline void atomic_clear(uint32_t *addr, uint32_t bits) +{ + uint32_t psw = get_psw(); + asm volatile ("setgie.d"); + *addr &= ~bits; + set_psw(psw); +} + +static inline void atomic_or(uint32_t *addr, uint32_t bits) +{ + uint32_t psw = get_psw(); + asm volatile ("setgie.d"); + *addr |= bits; + set_psw(psw); +} + +static inline void atomic_add(uint32_t *addr, uint32_t value) +{ + uint32_t psw = get_psw(); + asm volatile ("setgie.d"); + *addr += value; + set_psw(psw); +} + +static inline void atomic_sub(uint32_t *addr, uint32_t value) +{ + uint32_t psw = get_psw(); + asm volatile ("setgie.d"); + *addr -= value; + set_psw(psw); +} + +static inline uint32_t atomic_read_clear(uint32_t *addr) +{ + uint32_t val; + uint32_t psw = get_psw(); + asm volatile ("setgie.d"); + val = *addr; + *addr = 0; + set_psw(psw); + return val; +} +#endif /* __CROS_EC_ATOMIC_H */ |