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| author | Dino Li <Dino.Li@ite.com.tw> | 2017-05-26 10:11:25 +0800 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2017-05-29 21:49:05 -0700 |
| commit | c35fad0f2bc16fffe25dfe3b86f0df508d6d0b87 (patch) | |
| tree | 5044d9499277a8e9bb1997f7c10e522bd0dac8ea /core/nds32/init.S | |
| parent | a8cf9d92139eeebc412e2527d2c4329208af6901 (diff) | |
| download | chrome-ec-c35fad0f2bc16fffe25dfe3b86f0df508d6d0b87.tar.gz | |
chip: it83xx: add support for floating point unit
Because N8 CPU doesn't have floating point unit,
so we implement an extra floating point engine
(single-precision addition, subtraction, multiplication,
and division) into it8320 to improve performance of
floating point operation.
To make CPU's instruction compatible, we use register (DLMB)
to switch ALU (Arithmetic Logic Unit). eg:
Instruction 'ADD45' adds the contents of two registers then
writes the result to the source register.
But if we switch ALU to floating point operation mode,
this instruction will do a floating-point addition instead.
For the other FPU that we don't support as far,
we have to use soft float library routines of nds32.
Signed-off-by: Dino Li <dino.li@ite.com.tw>
BRANCH=none
BUG=none
TEST=add the following console command and test different
scenarios by changing variable a and b.
#define PRINTF_FLOAT(x) ((int)((x) * 1000.0f))
static int it83xx_fpu_test(int argc, char **argv)
{
volatile float a = 1.23f;
volatile float b = 4.56f;
volatile float c;
c = a + b;
ccprintf("__addsf3: (%d)\n", PRINTF_FLOAT(c));
c = a - b;
ccprintf("__subsf3: (%d)\n", PRINTF_FLOAT(c));
c = a * b;
ccprintf("__mulsf3: (%d)\n", PRINTF_FLOAT(c));
c = a / b;
ccprintf("__divsf3: (%d)\n", PRINTF_FLOAT(c));
return EC_SUCCESS;
}
DECLARE_CONSOLE_COMMAND(fpu, it83xx_fpu_test, "", "");
Change-Id: I4fc1c08d8c2376156bec9f098491187675c4a88f
Reviewed-on: https://chromium-review.googlesource.com/427640
Commit-Ready: Dino Li <Dino.Li@ite.com.tw>
Tested-by: Dino Li <Dino.Li@ite.com.tw>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Diffstat (limited to 'core/nds32/init.S')
| -rw-r--r-- | core/nds32/init.S | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/core/nds32/init.S b/core/nds32/init.S index 28dd1a5ca1..d278d4a899 100644 --- a/core/nds32/init.S +++ b/core/nds32/init.S @@ -192,6 +192,17 @@ excep_handler: la $r0, saved_regs + 4 smw.bim $r1, [$r0], $r10, 0 smw.bim $r15,[$r0], $r15, 0xF +#ifdef CONFIG_FPU + /* + * We have to restore ALU so that we can continue the next + * sequence if arithmetic instructions are used. + * (Apply to floating point division by zero) + */ + sethi $r4, 0x80 + ori $r4, $r4,0x9 + mtsr $r4, $dlmb + dsb +#endif /* put a sane stack pointer */ la $sp, stack_end /* add IPC, IPSW to the context */ |