summaryrefslogtreecommitdiff
path: root/core/nds32/task.c
diff options
context:
space:
mode:
authorDino Li <Dino.Li@ite.com.tw>2020-09-21 11:13:33 +0800
committerCommit Bot <commit-bot@chromium.org>2020-09-24 09:16:58 +0000
commit0542741e0e8727ae53bce47a1fd4459735056b53 (patch)
tree9763cda3eda742134912a49105aaf492622c24ee /core/nds32/task.c
parent1c3c2140f333f4a169f047fad8a780d0b71c2e5d (diff)
downloadchrome-ec-0542741e0e8727ae53bce47a1fd4459735056b53.tar.gz
it83xx: read_clear_int_mask() read and clear interrupt bit.
This change pulled the operation of interrupt disable into read_clear_int_mask(). Because riscv core supports instruction csrrc to atomic read and clear bit in CSR register. With this change, we won't need to separate operations of reading and clearing interrupt bit on riscv core. BUG=none BRANCH=none TEST=read_clear_int_mask() is able to disable interrupt and return saved interrupt bit on both nds32 and riscv cores. Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Change-Id: I871aab747b950b7948cdeb7911fcf8c09d55df5d Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2419739 Reviewed-by: Jett Rink <jettrink@chromium.org>
Diffstat (limited to 'core/nds32/task.c')
-rw-r--r--core/nds32/task.c21
1 files changed, 13 insertions, 8 deletions
diff --git a/core/nds32/task.c b/core/nds32/task.c
index f034c53f48..21bd8d5edd 100644
--- a/core/nds32/task.c
+++ b/core/nds32/task.c
@@ -473,11 +473,18 @@ uint32_t __ram_code task_wait_event_mask(uint32_t event_mask, int timeout_us)
return events & event_mask;
}
-uint32_t __ram_code get_int_mask(void)
+uint32_t __ram_code read_clear_int_mask(void)
{
- uint32_t ret;
- asm volatile ("mfsr %0, $INT_MASK" : "=r"(ret));
- return ret;
+ uint32_t int_mask, int_dis = BIT(30);
+
+ asm volatile(
+ "mfsr %0, $INT_MASK\n\t"
+ "mtsr %1, $INT_MASK\n\t"
+ "dsb\n\t"
+ : "=&r"(int_mask)
+ : "r"(int_dis));
+
+ return int_mask;
}
void __ram_code set_int_mask(uint32_t val)
@@ -526,18 +533,16 @@ void task_disable_task(task_id_t tskid)
void __ram_code task_enable_irq(int irq)
{
- uint32_t int_mask = get_int_mask();
+ uint32_t int_mask = read_clear_int_mask();
- interrupt_disable();
chip_enable_irq(irq);
set_int_mask(int_mask);
}
void __ram_code task_disable_irq(int irq)
{
- uint32_t int_mask = get_int_mask();
+ uint32_t int_mask = read_clear_int_mask();
- interrupt_disable();
chip_disable_irq(irq);
set_int_mask(int_mask);
}