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| author | Dino Li <dino.li@ite.com.tw> | 2015-09-12 15:06:33 +0800 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2015-09-18 01:25:52 -0700 |
| commit | ad8efdee3f6720d0f443963622babbc27ee25b53 (patch) | |
| tree | f21bfd007e85ac1c3714ac05593aea7c618b05ca /core/nds32/task.c | |
| parent | c935311856c644700d95a1a49bbac738b6571a9e (diff) | |
| download | chrome-ec-ad8efdee3f6720d0f443963622babbc27ee25b53.tar.gz | |
it8380dev: fix idle task and chip id
1. Fix system_get_chip_name() and system_get_chip_revision().
2. Fix EC doze mode.
3. Enable LPC cycle wake-up EC from doze / deep doze function.
Signed-off-by: Dino Li <dino.li@ite.com.tw>
BRANCH=none
BUG=none
TEST=1. console "version".
Chip: ite it8390 cx
2. EC doze mode is normally.
3. ectool "version" command x 2000.
Change-Id: I167dbfb965e557eb86ed83f45a945e4315f5fa9f
Reviewed-on: https://chromium-review.googlesource.com/299110
Commit-Ready: Dino Li <dino.li@ite.com.tw>
Tested-by: Dino Li <dino.li@ite.com.tw>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Diffstat (limited to 'core/nds32/task.c')
| -rw-r--r-- | core/nds32/task.c | 24 |
1 files changed, 23 insertions, 1 deletions
diff --git a/core/nds32/task.c b/core/nds32/task.c index bb62f5a725..5543d83cb1 100644 --- a/core/nds32/task.c +++ b/core/nds32/task.c @@ -11,6 +11,7 @@ #include "cpu.h" #include "irq_chip.h" #include "link_defs.h" +#include "registers.h" #include "task.h" #include "timer.h" #include "util.h" @@ -60,12 +61,33 @@ void __idle(void) */ cprints(CC_TASK, "idle task started"); +#if defined(CONFIG_LPC) && defined(CONFIG_IT83XX_LPC_ACCESS_INT) + IT83XX_WUC_WUESR4 = 0xff; + task_clear_pending_irq(IT83XX_IRQ_WKINTAD); + /* bit2, wake-up enable for LPC access */ + IT83XX_WUC_WUENR4 |= (1 << 2); +#endif + while (1) { +#if defined(CONFIG_LPC) && defined(CONFIG_IT83XX_LPC_ACCESS_INT) + BRAM_LPC_ACCESS = LPC_ACCESS_INT_BUSY; + /* LPC access interrupt pending. */ + if (IT83XX_WUC_WUESR4 & (1 << 2)) { + task_enable_irq(IT83XX_IRQ_WKINTAD); + continue; + } + BRAM_LPC_ACCESS = 0x00; + task_enable_irq(IT83XX_IRQ_WKINTAD); +#endif + + /* doze mode */ + IT83XX_ECPM_PLLCTRL = 0x00; + asm volatile ("dsb"); /* * Wait for the next irq event. This stops the CPU clock * (sleep / deep sleep, depending on chip config). */ - asm("standby no_wake_grant"); + asm("standby wake_grant"); } } #endif /* !CONFIG_LOW_POWER_IDLE */ |