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| author | Dino Li <dino.li@ite.com.tw> | 2015-06-16 12:01:08 +0800 |
|---|---|---|
| committer | ChromeOS Commit Bot <chromeos-commit-bot@chromium.org> | 2015-06-17 13:11:07 +0000 |
| commit | 3eb04bb57ed9c82b277fd16c0722665def273f1e (patch) | |
| tree | 270f02f3efeb877b1196a77f626bde04e84be966 /core/nds32 | |
| parent | cca70a517b21d32e45880d1296997436d026e7b7 (diff) | |
| download | chrome-ec-3eb04bb57ed9c82b277fd16c0722665def273f1e.tar.gz | |
it8380dev: add pmc control module
Add pmc(LPC ACPI) control module for emulation board.
Signed-off-by: Dino Li <dino.li@ite.com.tw>
BRANCH=none
BUG=none
TEST=1. 62h/66h port.
1-a. out 66h 80h, out 62h 00h, in 62h 02h
1-b. out 66h 81h, out 62h 01h, out 62h 55h
1-c. out 66h 80h, out 62h 01h, in 62h 55h
1-d. out 66h 80h, out 62h 02h, in 62h aah
2. H2RAM LPC I/O cycle 900h ~ 9FFh = DLM 0x8D900 ~ 0x8D9FF
and host read only.
3. 80h port, console command port80.
4. host command.
4-a. host request (LPC I/O 800h ~ 807h)
03 FD 00 00, 00 00 00 00
out 204h DAh, in 200h 00h
host response (LPC I/O 800h ~ 80Bh)
03 F7 00 00, 04 00 00 00, 02 00 00 00
4-b. host request
03 EE 01 00, 00 00 04 00, 01 02 03 04
out 204h DAh, in 200h 00h
host response
03 E5 00 00, 04 00 00 00, 05 05 05 05
Change-Id: I5c3bac66306dfba380548a74a64536ea606ddd3e
Reviewed-on: https://chromium-review.googlesource.com/269271
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Dino Li <dino.li@ite.com.tw>
Commit-Queue: Dino Li <dino.li@ite.com.tw>
Diffstat (limited to 'core/nds32')
| -rw-r--r-- | core/nds32/build.mk | 2 | ||||
| -rw-r--r-- | core/nds32/ec.lds.S | 17 |
2 files changed, 16 insertions, 3 deletions
diff --git a/core/nds32/build.mk b/core/nds32/build.mk index 810d5b8dd3..df89e3c8ac 100644 --- a/core/nds32/build.mk +++ b/core/nds32/build.mk @@ -10,6 +10,6 @@ CROSS_COMPILE?=nds32le-cros-elf- # CPU specific compilation flags -CFLAGS_CPU=-march=v3m -Os +CFLAGS_CPU+=-march=v3m -Os core-y=cpu.o init.o panic.o task.o switch.o diff --git a/core/nds32/ec.lds.S b/core/nds32/ec.lds.S index 8a8927f11a..57cf6512d3 100644 --- a/core/nds32/ec.lds.S +++ b/core/nds32/ec.lds.S @@ -4,10 +4,10 @@ */ #include "config.h" -#define FW_OFF_(section) CONFIG_FW_##section##_OFF +#define FW_OFF_(section) CONFIG_##section##_MEM_OFF #define FW_OFF(section) (CONFIG_FLASH_BASE + FW_OFF_(section)) -#define FW_SIZE_(section) CONFIG_FW_##section##_SIZE +#define FW_SIZE_(section) CONFIG_##section##_SIZE #define FW_SIZE(section) FW_SIZE_(section) @@ -18,6 +18,9 @@ MEMORY { FLASH (rx) : ORIGIN = FW_OFF(SECTION), LENGTH = FW_SIZE(SECTION) IRAM (rw) : ORIGIN = CONFIG_RAM_BASE, LENGTH = CONFIG_RAM_SIZE +#ifdef CONFIG_LPC + H2RAM (rw) : ORIGIN = CONFIG_H2RAM_BASE, LENGTH = CONFIG_H2RAM_SIZE +#endif } SECTIONS { @@ -207,6 +210,16 @@ SECTIONS BYTE(0xea); /* NOTHING MAY GO IN FLASH AFTER THIS! */ } >FLASH + +#ifdef CONFIG_LPC + .h2ram (NOLOAD) : { + . += CONFIG_H2RAM_HOST_LPC_IO_BASE; + *(.h2ram.pool.hostcmd) + . = ALIGN(256); + *(.h2ram.pool.acpiec) + } > H2RAM +#endif + #if !(defined(SECTION_IS_RO) && defined(CONFIG_FLASH)) /DISCARD/ : { *(.google) |