diff options
| author | Gwendal Grignou <gwendal@chromium.org> | 2019-03-11 15:57:52 -0700 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2019-03-26 04:42:55 -0700 |
| commit | bb266fc26fc05d4ab22de6ad7bce5b477c9f9140 (patch) | |
| tree | f6ada087f62246c3a9547e649ac8846b0ed6d5ab /core/nds32 | |
| parent | 0bfc511527cf2aebfa163c63a1d028419ca0b0c3 (diff) | |
| download | chrome-ec-bb266fc26fc05d4ab22de6ad7bce5b477c9f9140.tar.gz | |
common: replace 1 << digits, with BIT(digits)
Requested for linux integration, use BIT instead of 1 <<
First step replace bit operation with operand containing only digits.
Fix an error in motion_lid try to set bit 31 of a signed integer.
BUG=None
BRANCH=None
TEST=compile
Change-Id: Ie843611f2f68e241f0f40d4067f7ade726951d29
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1518659
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Diffstat (limited to 'core/nds32')
| -rw-r--r-- | core/nds32/cpu.h | 2 | ||||
| -rw-r--r-- | core/nds32/panic.c | 2 | ||||
| -rw-r--r-- | core/nds32/task.c | 6 |
3 files changed, 5 insertions, 5 deletions
diff --git a/core/nds32/cpu.h b/core/nds32/cpu.h index f5e4353cc3..f81bbbdc03 100644 --- a/core/nds32/cpu.h +++ b/core/nds32/cpu.h @@ -11,7 +11,7 @@ #include <stdint.h> /* Process Status Word bits */ -#define PSW_GIE (1 << 0) /* Global Interrupt Enable */ +#define PSW_GIE BIT(0) /* Global Interrupt Enable */ #define PSW_INTL_SHIFT 1 /* Interrupt Stack Level */ #define PSW_INTL_MASK (0x3 << PSW_INTL_SHIFT) diff --git a/core/nds32/panic.c b/core/nds32/panic.c index 4c855b5c06..3dabc1d2f0 100644 --- a/core/nds32/panic.c +++ b/core/nds32/panic.c @@ -174,7 +174,7 @@ static void print_panic_information(uint32_t *regs, uint32_t itype, panic_printf("Exception type: General exception [%s]\n", itype_exc_type[(itype & 0xf)]); panic_printf("Exception is caused by %s\n", - itype_inst[(itype & (1 << 4))]); + itype_inst[(itype & BIT(4))]); } #endif } diff --git a/core/nds32/task.c b/core/nds32/task.c index f713c52442..7cd9049733 100644 --- a/core/nds32/task.c +++ b/core/nds32/task.c @@ -214,7 +214,7 @@ static inline task_ *__task_id_to_ptr(task_id_t id) void __ram_code interrupt_disable(void) { /* Mask all interrupts, only keep division by zero exception */ - uint32_t val = (1 << 30); + uint32_t val = BIT(30); asm volatile ("mtsr %0, $INT_MASK" : : "r"(val)); asm volatile ("dsb"); } @@ -222,7 +222,7 @@ void __ram_code interrupt_disable(void) void __ram_code interrupt_enable(void) { /* Enable HW2 ~ HW15 and division by zero exception interrupts */ - uint32_t val = ((1 << 30) | 0xFFFC); + uint32_t val = (BIT(30) | 0xFFFC); asm volatile ("mtsr %0, $INT_MASK" : : "r"(val)); } @@ -600,7 +600,7 @@ static void ivic_init_irqs(void) * bit0 @ INT_CTRL = 0, * Interrupts still keep programmable priority level. */ - set_int_ctrl((get_int_ctrl() & ~(1 << 0))); + set_int_ctrl((get_int_ctrl() & ~BIT(0))); /* * Re-enable global interrupts in case they're disabled. On a reboot, |