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| author | tim <tim2.lin@ite.corp-partner.google.com> | 2019-03-28 14:08:15 +0800 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2019-03-30 20:59:39 -0700 |
| commit | 6a7c59affa6aba2af814a45f6f49908d22e2fa04 (patch) | |
| tree | 92e5c77dda843e1e1eae9eabafdb2650d23870fa /core/nds32 | |
| parent | 101ef9c869d483307eb9325ec82a97f606e9caca (diff) | |
| download | chrome-ec-6a7c59affa6aba2af814a45f6f49908d22e2fa04.tar.gz | |
it83xx/i2cs: add i2c slave function
The I2C function of IT8320 is used as the slave.
The slave channel A can support 16-byte FIFO for
read and write data. The enhanced I2C channel D,
E and F can support read and write 256-byte data
by DMA mode.
When master transmits data to slave, the interrupt
signal will generate, and the data will be saved
to buffer.
BUG=none
BRANCH=none
TEST=none
Change-Id: I167215352119ec11dfd96eb1f33abc1e2111dead
Signed-off-by: tim <tim2.lin@ite.corp-partner.google.com>
Reviewed-on: https://chromium-review.googlesource.com/1488273
Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com>
Tested-by: Tim2 Lin <tim2.lin@ite.corp-partner.google.com>
Reviewed-by: Jett Rink <jettrink@chromium.org>
Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Diffstat (limited to 'core/nds32')
| -rw-r--r-- | core/nds32/ec.lds.S | 11 |
1 files changed, 9 insertions, 2 deletions
diff --git a/core/nds32/ec.lds.S b/core/nds32/ec.lds.S index 659270c5b4..bb115ed8df 100644 --- a/core/nds32/ec.lds.S +++ b/core/nds32/ec.lds.S @@ -21,7 +21,7 @@ MEMORY { FLASH (rx) : ORIGIN = FW_OFF(SECTION), LENGTH = FW_SIZE(SECTION) IRAM (rw) : ORIGIN = CONFIG_RAM_BASE, LENGTH = CONFIG_RAM_SIZE -#ifdef CONFIG_HOSTCMD_X86 +#if defined(CONFIG_HOSTCMD_X86) || defined(CONFIG_I2C_SLAVE) H2RAM (rw) : ORIGIN = CONFIG_H2RAM_BASE, LENGTH = CONFIG_H2RAM_SIZE #endif } @@ -237,14 +237,21 @@ SECTIONS __image_size = LOADADDR(.data) + SIZEOF(.data) - FW_OFF(SECTION); -#ifdef CONFIG_HOSTCMD_X86 +#if defined(CONFIG_HOSTCMD_X86) || defined(CONFIG_I2C_SLAVE) .h2ram (NOLOAD) : { . += CONFIG_H2RAM_HOST_LPC_IO_BASE; *(.h2ram.pool.hostcmd) . = ALIGN(256); *(.h2ram.pool.acpiec) +#ifdef CONFIG_I2C_SLAVE + . = ALIGN(256); + *(.h2ram.pool.i2cslv) +#endif + __h2ram_end = .; } > H2RAM #endif + ASSERT((__h2ram_end) <= (CONFIG_H2RAM_BASE + CONFIG_H2RAM_SIZE), + "Not enough space for h2ram section.") #if !(defined(SECTION_IS_RO) && defined(CONFIG_FLASH)) /DISCARD/ : { |