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| author | Nicolas Boichat <drinkcat@chromium.org> | 2021-01-06 10:19:09 +0800 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2021-01-11 04:03:38 +0000 |
| commit | a0ec62ec5a7009c6b5a3507eae8615e674d1567b (patch) | |
| tree | ee3c3d38c4367d691987ba75e511bbf31ec8818a /core/riscv-rv32i | |
| parent | 23073aa336343ab0a2fec8e60a861a07d40d2f7d (diff) | |
| download | chrome-ec-a0ec62ec5a7009c6b5a3507eae8615e674d1567b.tar.gz | |
Revert "core/riscv-rv32i: Add exception_panic"
This reverts commit b3584dd1ea0b11c269424ab7693cb9609b15e568.
We found a more efficient way to trap integer division by zero,
so this code is technically not required anymore.
BRANCH=none
BUG=b:173969773
TEST=make buildall
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Change-Id: I3a89ab17477258c46a701935af121c3a4b0d41b1
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2612227
Commit-Queue: Tzung-Bi Shih <tzungbi@chromium.org>
Reviewed-by: Tzung-Bi Shih <tzungbi@chromium.org>
Reviewed-by: Eric Yilun Lin <yllin@chromium.org>
Diffstat (limited to 'core/riscv-rv32i')
| -rw-r--r-- | core/riscv-rv32i/cpu.h | 4 | ||||
| -rw-r--r-- | core/riscv-rv32i/panic.c | 19 |
2 files changed, 7 insertions, 16 deletions
diff --git a/core/riscv-rv32i/cpu.h b/core/riscv-rv32i/cpu.h index 94d6db4e81..e46b893ad6 100644 --- a/core/riscv-rv32i/cpu.h +++ b/core/riscv-rv32i/cpu.h @@ -21,7 +21,6 @@ #ifndef __ASSEMBLER__ #include <stdint.h> -#include <stdnoreturn.h> /* write Exception Program Counter register */ static inline void set_mepc(uint32_t val) @@ -47,9 +46,6 @@ static inline uint32_t get_mcause(void) return ret; } -/* Trigger a panic. */ -noreturn void exception_panic(uint32_t reason, uint32_t info); - /* Generic CPU core initialization */ void cpu_init(void); extern uint32_t ec_reset_lp; diff --git a/core/riscv-rv32i/panic.c b/core/riscv-rv32i/panic.c index cc95eb19a4..3d8cec1b06 100644 --- a/core/riscv-rv32i/panic.c +++ b/core/riscv-rv32i/panic.c @@ -33,17 +33,6 @@ static const char * const exc_type[16] = { }; #endif /* CONFIG_DEBUG_EXCEPTIONS */ -void exception_panic(uint32_t reason, uint32_t info) -{ - asm volatile ("mv s0, %0" : : "r"(reason)); - asm volatile ("mv s1, %0" : : "r"(info)); - if (in_interrupt_context()) - asm("j excep_handler"); - else - asm("ebreak"); - __builtin_unreachable(); -} - #ifdef CONFIG_SOFTWARE_PANIC /* General purpose register (s0) for saving software panic reason */ #define SOFT_PANIC_GPR_REASON 11 @@ -52,7 +41,13 @@ void exception_panic(uint32_t reason, uint32_t info) void software_panic(uint32_t reason, uint32_t info) { - exception_panic(reason, info); + asm volatile ("mv s0, %0" : : "r"(reason)); + asm volatile ("mv s1, %0" : : "r"(info)); + if (in_interrupt_context()) + asm("j excep_handler"); + else + asm("ebreak"); + __builtin_unreachable(); } void panic_set_reason(uint32_t reason, uint32_t info, uint8_t exception) |