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authorDino Li <Dino.Li@ite.com.tw>2020-11-13 10:01:33 +0800
committerCommit Bot <commit-bot@chromium.org>2020-11-18 02:57:08 +0000
commit1dcfc09283df045a0071d549d90de04bd90a60f0 (patch)
treee3c6b3b18a95cab251b79ede559f401e0983c25d /core
parenteb665ee6e1768177dacfa0cadfee783ad8a5d09a (diff)
downloadchrome-ec-1dcfc09283df045a0071d549d90de04bd90a60f0.tar.gz
it83xx: pull more functions into __ram_code section
Because we have space in the section, so we pulled more functions into the section. If a function is cached in __ram_code section (static cache), we can save latency of fetching code of the function from flash. (Fetching 64 bytes code from flash takes about 4us latency) BUG=none BRANCH=none TEST=buildall. Asurada and Drawcia are both able to boot to kernel. Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Change-Id: I8b413bd577c4e5b73a5c67018d17955da1ed0c55 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2535899 Reviewed-by: Diana Z <dzigterman@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
Diffstat (limited to 'core')
-rw-r--r--core/nds32/switch.S3
-rw-r--r--core/riscv-rv32i/switch.S3
2 files changed, 4 insertions, 2 deletions
diff --git a/core/nds32/switch.S b/core/nds32/switch.S
index b891aeb2a5..631b0e0fe2 100644
--- a/core/nds32/switch.S
+++ b/core/nds32/switch.S
@@ -8,7 +8,7 @@
#include "config.h"
#include "cpu.h"
-.text
+.section .ram_code
/**
* Task context switching
@@ -73,6 +73,7 @@ __switch_task:
/* restore PC and PSW */
iret
+.text
/**
* Start the task scheduling.
*
diff --git a/core/riscv-rv32i/switch.S b/core/riscv-rv32i/switch.S
index d6c00b8591..b7750975fd 100644
--- a/core/riscv-rv32i/switch.S
+++ b/core/riscv-rv32i/switch.S
@@ -8,7 +8,7 @@
#include "config.h"
#include "cpu.h"
-.text
+.section .ram_code
/**
* Task context switching
@@ -142,6 +142,7 @@ __switch_task:
add sp, t3, zero
j __irq_exit
+.text
/**
* Start the task scheduling.
*/